LTC3370 datasheet(11/22 Pages) AD

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LTC3315B

Rev. 0

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The sleep time decreases as load current increases. In

Burst Mode operation, the regulator will burst at light

loads whereas at higher loads it will operate in constant

frequency PWM mode.

Synchronizing the Oscillator to an External Clock

Selection of the operating frequency is a trade-off between

efficiency and component size. High frequency operation

allows the use of smaller inductor and capacitor values

and improves transient response. Operation at lower

frequencies improves efficiency by reducing switching

losses but requires larger inductance and/or capaci-

tance values to maintain low output voltage ripple. The

LTC3315B operates at a default frequency of 6MHz.

The LTC3315B’s internal oscillator is synchronized

through an internal PLL circuit to an external frequency by

applying a square wave clock signal to the MODE/SYNC

pin. During synchronization, the Buck 1 PMOS turn-on is

locked to the rising edge of the external frequency source.

Buck 2 will be 180° out of phase with respect to Buck 1.

While syncing, the buck switching regulators operate in

forced continuous mode. The synchronization frequency

range is 3MHz to 10MHz.

After detecting an external clock on the SYNC pin, the

internal PLL starts up at the default frequency. The inter-

nal PLL then gradually adjusts its operating frequency to

match the frequency and phase of the SYNC signal.

When the external clock is removed the LTC3315B will

detect the absence of the external clock within approxi-

mately 10µs. During this time it will continue to provide

clock cycles. Once the external clock removal has been

detected, the oscillator will gradually adjust its operating

frequency back to the default.

Power Failure Reporting Via PGOOD Pin

Power failure faults are reported via the PGOOD pin.

Both buck switching regulators have an internal power

good (PGOOD) signal and if a buck is enabled its internal

PGOOD signal must be high for the PGOOD pin to be high.

OPERATION

When the regulated output voltage of an enabled buck

rises above 98% of its programmed value, the PGOOD

signal transitions high. If the regulated output voltage

subsequently falls below 97% of its programmed value,

the PGOOD signal is pulled low. If either enabled buck’s

internal PGOOD signal stays low for greater than 120μs,

then the PGOOD pin is pulled low, indicating to a micro-

processor that a power fault has occurred. The 120μs

filter time prevents the pin from being pulled low during a

transient event. In addition, whenever PGOOD transitions

high there will be a 120μs assertion delay.

The LTC3315B also reports overvoltage conditions at

the PGOOD pin. If either enabled buck regulator’s out-

put voltage rises above 110% of its programmed value,

the PGOOD pin is pulled low after 120μs. Similarly, if all

enabled outputs that are overvoltage subsequently fall

below 107.8% of their programmed value, the PGOOD

pin transitions high again after 120μs.

An error condition that pulls the PGOOD pin low is not

latched. When the error condition goes away, the PGOOD

pin is released and is pulled high if no other error condi-

tion exists. PGOOD is also pulled low in the following

scenarios: if neither buck switching regulator is enabled,

if VIN is below the UVLO threshold, or if the LTC3315B is

over temperature (see below).

Output Overvoltage Protection

During an output overvoltage event, when the FB pin

voltage is greater than 110% of its regulated value, the

LTC3315B PMOS will be turned off immediately.

An output overvoltage event should not happen under

normal operating conditions.

Overtemperature Protection

To prevent thermal damage, the LTC3315B incorporates

an overtemperature (OT) function. When the LTC3315B

die temperature reaches 165°C (typical, not tested) all

enabled buck switching regulators are shut down and

remain in shutdown until the die temperature falls to

160°C (typical, not tested).

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