LTC3370 datasheet(13/24 Pages) AD

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LTC3315A

Rev. A

For more information www.analog.com

OPERATION

APPLICATIONS INFORMATION

Output Voltage Soft-Start

Softstartingtheoutputpreventscurrentsurgeontheinput

supply and/or output voltage overshoot. During soft-start,

the output voltage will proportionally track an internal

voltage ramp. An active pull-down circuit discharges that

internal voltage in the case of fault conditions. The ramp

will restart when the fault is cleared. Fault conditions that

initiate the soft-start ramp are the VIN voltage falling too

low or thermal shutdown.

Recovery from an output short-circuit (see below) may

involve another soft-start cycle if the FB voltage falls more

than 120mV (typical) below regulation. During such a

recovery, the FB voltage will quickly charge up to 120mV

(typical) and then follow the soft-start ramp until regula-

tion is reached.

Dropout Operation

As the input supply voltage approaches the output volt-

age, the duty cycle increases toward 100%. Further reduc-

tion of the supply voltage forces the PMOS to remain on

for more than one cycle, eventually reaching 100% duty

cycle. The output voltage will then be determined by the

input voltage minus the DC voltage drop across the inter-

nal PMOS and the inductor.

Low Supply Operation

The LTC3315A is designed to operate down to an input

supply voltage of 2.25V. An important thermal design

consideration is that the RDS(ON) of the power switches

increases at low input. Consider the worst case LTC3315A

power dissipation and die junction temperature at the low-

est input voltage.

Output Short-Circuit Protection and Recovery

The peak inductor current level at which the current com-

parator shuts off the PMOS is controlled by the error

amplifier. When the output current increases, the error

amplifier raises the internal VC voltage until the average

inductor current matches the load current. The LTC3315A

clamps the maximum internal VC voltage, thereby limiting

the peak inductor current.

When the output is shorted to ground, the inductor cur-

rent decays very slowly during the downslope because

the voltage across the inductor is low. To keep the induc-

tor current in control a secondary limit is imposed on

the valley of the inductor current. If the inductor cur-

rent measured through the NMOS remains greater than

IVALLEY at the end of the cycle, the PMOS will be held

off. Subsequent switching cycles will be skipped until the

inductor current falls below IVALLEY.

Buck Switching Regulator Output Voltage and

Feedback Network

The output voltage of the buck switching regulators is

programmed by a resistor divider connected from the

switching regulator’s output to ground and is given by:

VOUT = VFB 1+

⎛

⎝

⎜

⎞

⎠

⎟

(1)

as shown in Figure 1 where VFB = 500mV. Typical val-

ues for R1 range from 40kΩ to 1MΩ. 1% resistors are

recommended to maintain output voltage accuracy. The

buck regulator transient response may improve with

an optional phase lead capacitor CFF that helps cancel

the pole created by the feedback resistors and the input

capacitance of the FB pin. Experimentation with capaci-

tor values between 2pF and 22pF may improve transient

response. The values used in the typical application cir-

cuits are a good starting point.

Figure 1. Feedback Components

COUT

CFF

VOUT

3315ab F01

BUCK

SWITCHING

REGULATOR

(OPTIONAL)

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