74LS109A datasheet(1/4 Pages) ONSEMI

номер детали	74LS109A

подробное описание детали	LOW POWER SCHOTTKY

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производитель	ONSEMI [ON Semiconductor]

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December, 1999 – Rev. 6

1

Publication Order Number:

SN74LS109A/D

SN74LS109A

Dual JK Positive

Edge-Triggered Flip-Flop

The SN74LS109A consists of two high speed completely

independent transition clocked JK flip-flops. The clocking operation

is independent of rise and fall times of the clock waveform. The JK

design allows operation as a D flip-flop by simply connecting the J and

K pins together.

MODE SELECT – TRUTH TABLE

OPERATING MODE

INPUTS

OUTPUTS

OPERATING MODE

SD

CD

J

K

Q

Set

Reset (Clear)

*Undetermined

Load “1” (Set)

Hold

Toggle

Load “0” (Reset)

L

H

L

H

L

H

X

h

l

h

l

X

h

l

H

L

H

q

L

H

L

q

H

*

Both outputs will be HIGH while both SD and CD are LOW, but the output

states are unpredictable if SD and CD go HIGH simultaneously.

H, h = HIGH Voltage Level

L, I = LOW Voltage Level

X = Don’t Care

l, h (q) = Lower case letters indicate the state of the referenced input

i, h (q) = (or output) one set-up time prior to the LOW to HIGH clock transition.

GUARANTEED OPERATING RANGES

Symbol

Parameter

Min

Typ

Max

Unit

VCC

Supply Voltage

4.75

5.0

5.25

V

TA

Operating Ambient

Temperature Range

0

25

70

°C

IOH

Output Current – High

– 0.4

mA

IOL

Output Current – Low

8.0

mA

LOW

POWER

SCHOTTKY

Device

Package

Shipping

ORDERING INFORMATION

SN74LS109AN

16 Pin DIP

2000 Units/Box

SN74LS109AD

16 Pin

SOIC

D SUFFIX

CASE 751B

http://onsemi.com

2500/Tape & Reel

PLASTIC

N SUFFIX

CASE 648

16

1

16

1

Аналогичный номер детали - 74LS109A

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Texas Instruments	74LS109	409Kb / 12P	DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR 2022

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Аналогичное описание - 74LS109A

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