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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MAS3529F датащи(PDF) 46 Page - Micronas |
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MAS3529F датащи(HTML) 46 Page - Micronas |
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46 / 92 page  MAS 35x9F DATA SHEET 46 June 30, 2004; 6251-505-1DS Micronas 3.4.3. Codec Registers Table 3–16: Codec control registers on I2C subaddress 6C hex Register Address (hex) Function Name CONVERTER CONFIGURATION 00 00 Audio Codec Configuration 0 dB is related to the D/A full-scale output voltage Please refer to (see Section 4.6.3. on page 81). bit[15:12] A/D converter left amplifier gain = n*1.5 −3 [dB] bit[11:8] A/D converter right amplifier gain = n*1.5 −3 [dB] 1111 +19.5 dB 1110 +18.0 dB ... ... 0011 +1.5 dB 0010 0.0 dB 0001 −1.5 dB 0000 − 3.0 dB bit[7:4] Microphone amplifier gain = n*1.5+21 [dB] 1111 +43.5 dB 1110 +42.0 dB ... ... 0001 +22.5 dB 0000 +21.0 dB bit[3] Input selection for left A/D converter channel 0 line-in 1 microphone bit[2] Enable left A/D converter1) bit[1] Enable right A/D converter1) bit[0] Enable D/A converter1) CONV_CONF 1) The generation of the internal DC reference voltage for the D/A converter is also controlled with this bit. In order to avoid click noise, the reference voltage at pin AGNDC should have reached a near ground potential before repowering the D/A converter after a short down phase. Alternatively, at least one of the A/D converters (bits[2] or [1]) should remain set during short power-down phases of the D/A. Then the DC reference voltage generation for the D/A converter will not be interrupted. |
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