ADSP-21486KSWZ-2AB datasheet(46/71 Pages) AD

номер детали	ADSP-21486KSWZ-2AB

подробное описание детали	SHARC Processor

PDF	71 Pages

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производитель	AD [Analog Devices]

домашняя страница	http://www.analog.com

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46 / 71 page

Rev. H

Page 46 of 71

February 2020

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Figure 30 shows the default I2S-justified mode. The frame sync

is low for the left channel and HI for the right channel. Data is

valid on the rising edge of serial clock. The MSB is left-justified

to the frame sync transition but with a delay.

Figure 31 shows the left-justified mode. The frame sync is high

for the left channel and low for the right channel. Data is valid

on the rising edge of serial clock. The MSB is left-justified to the

frame sync transition with no delay.

Table 44. S/PDIF Transmitter I2S Mode

Parameter

Nominal

Unit

Timing Requirement

tI2SD

Frame Sync to MSB Delay in I2S Mode

SCLK

Figure 30. I2S-Justified Mode

MSB

LEFT/RIGHT CHANNEL

LSB

MSB–1 MSB–2

LSB+2

LSB+1

DAI_P20–1

SCLK

DAI_P20–1

SDATA

tI2SD

Table 45. S/PDIF Transmitter Left-Justified Mode

Parameter

Nominal

Unit

Timing Requirement

tLJD

Frame Sync to MSB Delay in Left-Justified Mode

SCLK

Figure 31. Left-Justified Mode

MSB

LEFT/RIGHT CHANNEL

LSB

MSB–1 MSB–2

LSB+2

LSB+1

DAI_P20–1

SCLK

DAI_P20–1

SDATA

tLJD

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