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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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S25FL002D0FMAI011 датащи(PDF) 13 Page - SPANSION |
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S25FL002D0FMAI011 датащи(HTML) 13 Page - SPANSION |
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13 / 38 page  June 9, 2004 30167A+1 S25FL Family (Serial Peripheral Interface) 13 Pre limin ary I n f o r m a t ion Instructions All instructions, addresses, and data are shifted in and out of the device, starting with the most significant bit. Serial Data Input (SI) is sampled on the first rising edge of Serial Clock (SCK) after Chip Select (CS#) is driven Low. Then, the one- byte instruction code must be shifted in to the device, most significant bit first, on Serial Data Input (SI), each bit being latched on the rising edges of Serial Clock (SCK). The instruction set is listed in Table 5. Every instruction sequence starts with a one-byte instruction code. Depending on the instruction, this might be followed by address bytes, or by data bytes, or by both or none. Chip Select (CS#) must be driven High after the last bit of the in- struction sequence has been shifted in. In the case of a Read Data Bytes (READ), Read Status Register (RDSR), Fast Read (FAST_READ) and Read ID (READ_ID), the shifted-in instruction sequence is fol- lowed by a data-out sequence. Chip Select (CS#) can be driven High after any bit of the data-out sequence is being shifted out to terminate the transaction. In the case of a Page Program (PP), Sector Erase (SE), Bulk Erase (BE), Write Status Register (WRSR), Write Enable (WREN), or Write Disable (WRDI) instruc- tion, Chip Select (CS#) must be driven High exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. That is, Chip Select (CS#) must driven High when the number of clock pulses after Chip Select (CS#) being driven Low is an exact multiple of eight. All attempts to access the memory array during a Write Status Register cycle, Program cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cycle continues unaffected Table 5. Instruction Set. Instruction Description One-Byte Instruction Code Address Bytes Dummy Byte Data Bytes Status Register Operations WREN Write Enable 06H (0000 0110) 0 0 0 WRDI Write Disable 04H (0000 0100) 0 0 0 WRSR Write to Status Register 01H (0000 0001) 0 0 1 RDSR Read from Status Register 05H (0000 0101) 0 0 1 to Infinity Read Operations READ Read Data Bytes 03H (0000 0011) 3 0 1 to Infinity FAST_READ Read Data Bytes at Higher Speed 0BH (0000 1011) 3 1 1 to Infinity READ_ID Read ID ABH (1010 1011) 0 3 1 to Infinity Erase Operations SE Sector Erase D8H (1101 1000) 3 0 0 BE Bulk (Chip) Erase C7H (1100 0111) 0 0 0 Program Operations PP Page Program 02H (0000 0010) 3 0 1 to 256 Dummy Power Savings Mode Operations SP Software Protect B9H (1011 1001) 0 0 0 RES Release from Software Protect ABH (1010 1011) 0 0 0 Release from Software Protect and Read Electronic Signature ABH (1010 1011) 0 3 1 to Infinity |
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