MCP3551-ESLASHMS datasheet(18/30 Pages) MICROCHIP

18 / 30 page

MCP3551/3

DS21950B-page 18

5.3

Single Conversion Mode

If a rising edge of Chip Select (CS) occurs during tCONV,

a subsequent conversion will not take place and the

device will enter low-power Shutdown mode after

tCONV completes. This is referred to as Single

Conversion mode. This operation is demonstrated in

Figure 5-3. Note that a falling edge of CS during the

same conversion that detected a rising edge, as in

Figure 5-2, will not initiate a new conversion. Once a

rising edge is seen, the device will enter Sleep, then

Shutdown mode. Once the device has been put into

Single Conversion mode, the data must be clocked out

in order for a new conversion to take place. A

subsequent falling edge on CS during Shutdown mode

will not initiate a new conversion, unless the prior

conversion data has been clocked out of the device.

After the final data bit has been clocked out on the 25th

clock, the SDO/RDY pin will go active-high.

5.3.1

READY FUNCTION OF SDO/RDY

PIN, SINGLE CONVERSION MODE

At every falling edge of CS during the internal conver-

sion, the state of the internal conversion is latched on

the SDO/RDY pin to give ready or busy information. A

High state means the device is currently performing an

internal conversion and data cannot be clocked out. A

Low state means the device has finished its conversion

and the data is ready for retrieval on the falling edge of

SCK. This operation is demonstrated in Figure 5-4.

Note that the device has been put into Single

Conversion mode with the first rising edge of CS.

FIGURE 5-4:

RDY Functionality in Single

Conversion Mode.

5.4

Continuous Conversion Mode

If no rising edge of CS occurs during any given conver-

sion per Figure 5-2, a subsequent conversion will take

place and the contents of the previous conversion will

be overwritten. This operation is demonstrated in

Figure 5-5. Once conversion output data has started to

be clocked out, the output buffer is not refreshed until

all 24 bits have been clocked. A complete read must

occur in order to read the next conversion in this mode.

The subsequent conversion data to be read will then be

the most recent conversion. The conversion time is

fixed and cannot be shortened by the rising edge of CS.

This rising edge will place the part in Shutdown mode

and all conversion data will be lost.

The transfer of data from the SINC filter to the output

buffer is demonstrated in Figure 5-5. If the previous

conversion data is not clocked out of the device, it will

be lost and replaced by the new conversion. When the

device is in Continuous Conversion mode, the most

recent conversion data is always present at the output

FIGURE 5-5:

Most Current Continuous

Conversion Mode Data.

If a conversion is in process, it cannot be terminated

with the rising edge of CS. SDO/RDY must first

transition to a Low state, which will indicate the end of

conversion.

5.4.1

READY FUNCTION OF SDO/RDY

PIN IN CONTINUOUS CONVERSION

MODE

The device enters Continuous Conversion mode if no

rising edge of CS is seen during tCONV and consecu-

tive conversions ensue. SDO/RDY will be high,

indicating that a conversion is in process. When a

conversion is complete, SDO/RDY will change to a

Low state. With the Low state of SDO/RDY after this

first conversion, the conversion data can be accessed

with the combination of SCK and SDO/RDY. If the data

ready event happens during the clocking out of the

data, the data ready bit will be displayed after the

complete 24-bit word communication (i.e., the data

ready event will not interrupt a data transfer).

Note:

The Ready state is latched on each falling

edge of CS and will not dynamically

update if CS is held low. CS must be

toggled high thru low.

tCONV

Int. Osc

SDO/RDY

Hi-Z

tCONV

Int. Osc

SCK & SDO/RDY

Conversion B data is clocked

out of the device here.

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