6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)

MIN

MAX

UNIT

Voltage across pins 2 (+) and 1(–)

6

V

Current through the device

450

µA

–65

155

°C

–65

155

°C

(1)

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or anyother conditions beyond those indicated under

Recommended OperatingConditions. Exposure to absolute-maximum-rated conditions for extended periods mayaffect device

reliability.

6.2 ESD Ratings

VALUE

UNIT

Electrostatic discharge

Human-body model (HBM) per per AEC Q100-002 (1)

HBM classification level 2

±2000

V

Charged device model (CDM), per AEC Q100- 011

CDM classification level C6

±1000

(1)

AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX UNIT

Voltage across pins 2 (+) and 1 (–)

0

5.5

V

Current through the device

0

40

µA

Operating free-air temperature (X1SON/DEC Package)

–40

125

°C

Operating free-air temperature (SOT-5X3/DYA Package)

–40

150

°C

6.4 Thermal Information

THERMAL METRIC (1)

TMP63-Q1

Units

DEC (X1SON) DYA (SOT-5X3)

2 PINS

2 PINS

Junction-to-ambient thermal resistance(2) (3)

443.4

742.9

°C/W

Junction-to-case (top) thermal resistance

195.7

315.8

°C/W

Junction-to-board thermal resistance

254.6

506.2

°C/W

Junction-to-top characterization parameter

19.9

109.3

°C/W

Junction-to-board characterization parameter

254.5

500.4

°C/W

Junction-to-case (bot) thermal resistance

–

–

°C/W

(1)

For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

(2)

board as specified in JESD51-7, in an environment described in JESD51-2. Exposed pad packages assume that thermal vias are

included in the PCB, per JESD 51-5.

(3)

Changes in output due to self heating can be computed by multiplying the internal dissipation by the thermal resistance.

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TMP63-Q1

SNIS215C – JANUARY 2020 – REVISED SEPTEMBER 2020

Copyright © 2020 Texas Instruments Incorporated

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