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FS32K112BHTXVLUTR датащи(PDF) 27 Page - NXP Semiconductors |
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FS32K112BHTXVLUTR датащи(HTML) 27 Page - NXP Semiconductors |
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27 / 100 page ![]() The following table shows the power consumption targets for S32K148 in various mode of operations measure at 3.3 V. Table 15. Power consumption at 3.3 V Chip/Device Ambient Temperature (°C) RUN@80 MHz (mA) HSRUN@112 MHz (mA)1 Peripherals enabled + QSPI Peripherals enabled + ENET + SAI Peripherals enabled + QSPI Peripherals enabled + ENET + SAI S32K148 25 Typ 67.3 79.1 89.8 105.5 85 Typ 67.4 79.2 95.6 105.9 Max 82.5 88.2 109.7 117.4 105 Typ 68.0 79.8 96.6 106.7 Max 80.3 89.1 109.0 119.0 125 Max 83.5 94.7 NA 1. HSRUN mode must not be used at 125°C. Max ambient temperature for HSRUN mode is 105°C. 4.8 ESD handling ratings Symbol Description Min. Max. Unit Notes VHBM Electrostatic discharge voltage, human body model − 4000 4000 V 1 VCDM Electrostatic discharge voltage, charged-device model 2 All pins except the corner pins − 500 500 V Corner pins only − 750 750 V ILAT Latch-up current at ambient temperature of 125 °C − 100 100 mA 3 1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components. 3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test. 4.9 EMC radiated emissions operating behaviors EMC measurements to IC-level IEC standards are available from NXP on request. General S32K1xx Data Sheet, Rev. 12, 02/2020 NXP Semiconductors 27 |
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