ADGS1414DBCCZ datasheet(21/28 Pages) AD

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Data Sheet

ADGS1414D

Rev. 0 | Page 21 of 28

SCLK Count Error Detection

SCLK count error detection allows the user to detect if an incorrect

number of SCLK cycles are sent by the microcontroller or CPU.

When in address mode, with CRC disabled, 16 SCLK cycles are

expected. If 16 SCLK cycles are not detected, the SCLK count

error flag asserts in the error flags register. When less than

16 SCLK cycles are received by the device, a write to the register

map does not occur. When the ADGS1414D receives more

than 16 SCLK cycles, a write to the memory map still occurs at

the 16th SCLK rising edge, and the flag asserts in the error flags

cycles is 24. SCLK count error detection is enabled by default

and can be configured by the user through the error

configuration register.

Invalid Read and Write Address Error

An invalid read and write address error detects when a nonexistent

error asserts when a write to a read only register is attempted.

The invalid read and write address error flag asserts in the error

flags register when an invalid read and write address error occurs.

The invalid read and write address error is detected on the ninth

SCLK rising edge, which means a write to the register does not

occur when an invalid address is targeted. Invalid read and

write address error detection is enabled by default and can be

disabled by the user through the error configuration register.

CLEARING THE ERROR FLAGS REGISTER

To clear the error flags register, write the special 16-bit SPI

frame, 0x6CA9, to the device. This SPI command does not

trigger the invalid R/W address error. When CRC is enabled,

the user must also send the correct CRC byte for a successful

error clear command. At the 16th or 24th SCLK rising edge, the

error flags register resets to zero.

BURST MODE

The SPI can accept consecutive SPI commands without the need

to deassert the CS line, which is called burst mode. Burst mode

is enabled through the burst enable register. This mode uses the

same 16-bit command to communicate with the device. In

addition, the response of the device at SDO is still aligned with

the corresponding SPI command. Figure 41 shows an example

of SDI and SDO during burst mode.

The invalid read and write address and CRC error checking

functions operate similarly during burst mode as these error

checking functions do during address mode. However, SCLK

count error detection operates in a slightly different manner.

The total number of SCLK cycles within a given CS frame are

counted, and if the total is not a multiple of 16, or a multiple of

24 when CRC is enabled, the SCLK count error flag asserts.

Figure 41. Burst Mode Frame

SOFTWARE RESET

When in address mode, the user can initiate a software reset by

writing two consecutive SPI commands, 0xA3 followed by

0x05, targeting Register 0x0B. After a software reset, all register

values are set to default.

DAISY-CHAIN MODE

The connection of several ADGS1414D devices in a daisy-chain

configuration is possible, and Figure 42 illustrates this setup. All

devices share the same CS, SCLK, and VL line, whereas the SDO of

a device forms a connection to the SDI of the next device, creating

a shift register. In daisy-chain mode, SDO is an eight cycle delayed

version of SDI. When in daisy-chain mode, all commands target

the switch data register. Therefore, it is not possible to make

configuration changes while in daisy-chain mode.

Figure 42. Two ADGS1414D Devices Connected in a Daisy-Chain Configuration

SDO

COMMAND0[15:0]

RESPONSE0[15:0]

COMMAND1[15:0]

RESPONSE1[15:0]

COMMAND2[15:0]

RESPONSE2[15:0]

COMMAND3[15:0]

RESPONSE3[15:0]

SDI

SCLK

SDO

ADGS1414D

DEVICE 1

SPI

INTERFACE

SDO

ADGS1414D

DEVICE 2

SPI

INTERFACE

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