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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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L64734 датащи(PDF) 21 Page - LSI Computer Systems |
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L64734 датащи(HTML) 21 Page - LSI Computer Systems |
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21 / 48 page  L64733/L64734 Tuner and Satellite Receiver Chipset 21 Tuner Control Interface The Tuner Control interface contains signals that control the L64733 Tuner IC. FLCLK Filter Control Clock Output FLCLK is the output of a programmable integer value divider clocked by the demodulator sampling clock, PCLK. The division ratio can be programmed with register bits. The frequency of FLCLK multiplied by 16 is the 3 dB cutoff of the programmable low-pass filters on the L64733. INSEL RF Input Select Output When INSEL is asserted, the L64733 tuner selects the normal mode. When INSEL is deasserted, the L64733 selects the Loop-Through mode. Typical Operating Circuit Figure 7 is a diagram of a typical operating circuit for the chipset, including external components. Not all external components are shown. See the L64733/34 Evaluation Board User’s Guide for complete schematic details. |
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