IIS3DHHCTR datasheet(19/30 Pages) STMICROELECTRONICS

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7.3

INT2_CTRL (22h)

INT2 pin control register

Table 11. INT2_CTRL register

INT2_DRDY

INT2_BOOT

INT2_OVR

INT2_ FSS5

INT2_FTH

0 (1)

0(1)

1. This bit must be set to ‘0’ for the correct operation of the device.

INT2_DRDY

Accelerometer data ready on INT2 pin. Default value: 0

(0: disabled; 1: enabled)

INT2_ BOOT

Boot status available on INT2 pin. Default value: 0

(0: disabled; 1: enabled)

INT2_OVR

Overrun flag on INT2 pin. Default value: 0

(0: disabled; 1: enabled)

INT2_ FSS5

FSS5 full FIFO flag on INT2 pin. Default value: 0

(0: disabled; 1: enabled)

INT2_FTH

FIFO threshold flag on INT2 pin. Default value: 0

(0: disabled; 1: enabled)

7.4

CTRL_REG4 (23h)

Control register 4

Table 12. CTRL_REG4 register

DSP_LP_

TYPE

DSP_BW_

SEL

ST2

ST1

PP_OD_

INT2

PP_OD_

INT1

FIFO_EN

OFF_TCOMP

_EN

Table 13. CTRL_REG4 register description

DSP_LP_TYPE

Digital filtering selection. Default value: 0

(0: FIR Linear Phase; 1: IIR Nonlinear Phase)

DSP_BW_SEL

User-selectable bandwidth. Default value: 0

(0: 440 Hz typ.; 1: 235 Hz typ.)

ST [2:1]

Self-test enable. Default value: 00

(00: Self-test disabled; Other: See Table 14. Self-test mode selection)

PP_OD_INT2

Push-pull/open drain selection on INT2 pin. Default value: 0

(0: push-pull mode; 1: open drain mode)

PP_OD_INT1

Push-pull/open drain selection on INT1 pin. Default value: 0

(0: push-pull mode; 1: open drain mode)

FIFO_EN

FIFO memory enable. Default value: 0

(0: disabled; 1: enabled)

OFF_TCOMP_EN

Offset temperature compensation enable. Default value: 0

(0: disabled; 1: enabled)

IIS3DHHC

INT2_CTRL (22h)

DS12292 - Rev 3

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