ADMV4530 datasheet(32/59 Pages) AD

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ADMV4530

Data Sheet

Rev. A | Page 32 of 59

AUTOCALIBRATION LOCK TIME

The PLL lock time divides into a number of settings. The total

lock time for changing frequencies is the sum of three separate

times: synthesizer lock, VCO band selection, and PLL settling.

SYNTHESIZER LOCK TIMEOUT

The synthesizer lock timeout ensures that the VCO calibration

digital-to-analog converter (DAC), which forces the VCO tune

voltage (VVTUNE), has settled to a steady value for the band select

circuitry. The SYNTH_LOCK_TIMEOUT and the TIMEOUT

bits select the length of time the DAC is allowed to settle to the

final voltage before the VCO calibration process continues to

the next phase (VCO band selection). The PFD frequency is the

clock for this logic, and the duration is set by using the

following equation:

(SYNTH_LOCK_TIMEOUT × 1024 + TIMEOUT)/fPFD

where:

SYNTH_LOCK_TIMEOUT is programmed in Bits[4:0],

TIMEOUT is programmed in Bits[7:0], Register 0x031 and

Bits[1:0], Register 0x032.

The calculated time must be greater than or equal to 20 µs.

For the SYNTH_LOCK_TIMEOUT bits, the minimum value is 2,

and the maximum value is 31.

For TIMEOUT, the minimum value is 2, and the maximum

value is 1023.

VCO BAND SELECTION TIME

Use the VCO_BAND_DIV bits (Bits[7:0], Register 0x030) and

the fPFD to generate the VCO band selection clock (fBSC) as follows:

fBSC = (fPFD/VCO_BAND_DIV)

The calculated frequency must be less than 4 MHz.

Note that 16 clock cycles are required for one VCO core and

band calibration step and the total band selection process takes

11 steps, resulting in the following equation:

11 × (16 × VCO_BAND_DIV/fPFD)

The minimum value for VCO_BAND_DIV is 1, and the

maximum value is 255.

PLL SETTLING TIME

The time taken for the loop to settle is inversely proportional to

the low-pass filter bandwidth.

CHIP TEMPERATURE READ BACK

Chip temperature readback can provide information regarding

system temperature, which is useful for system compensation.

The ADMV4530 includes an analog-to-digital converter (ADC)

that enables reading the chip temperature. The ADC clock

(ADC_CLK) is generated from the phase frequency detector

clock (fPFD) with the following equations:

(

)

(

)

× 4 + 2

PFD

ADC_CLK

ADC_CLK_DIV

where ADC_CLK_DIV is stored in Register 0x035.

A valid reference signal is required to complete a conversion.

Target 100 kHz for ADC_CLK and calculate ADC_CLK_DIV

with the following equation:

– 2

100,000

PFD

ADC_CLK_DIV ceiling











If ADC_CLK_DIV is greater than 255, set these bits to 255.

The bits used for temperature readback are the following:

•

To read back the temperature, take the following steps:

1. Set ADC_ENABLE = 1 to enable the ADC.

2. Set ADC_CONVERSION = 1 to perform an ADC

conversion.

3. Wait 16 ADC_CLK cycles.

4. Set VCO_FSM_READBACK = 101 (skip this step if it is

already set).

5. Read the VCO_DATA_READBACK bits in Register

0x06E to read back the raw ADC output that corresponds

to the chip temperature (RAW_TEMP).

6. Set ADC_CONVERSION = 0 to disable the conversion.

7. Set ADC_ENABLE = 0 to disable the ADC, which prevents

any spurs generated by the ADC clock. Similarly, the

ADC_CLK_DISABLE bit can disable the ADC clock.

Perform Step 1 and Step 2 separately. However, Step 6 and

Step 7 can be completed together.

To calculate the approximate chip temperature in Celsius (°C),

use the following equation:

Chip Temperature = −100°C + RAW_TEMP

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