FS32K112BHTXVLFTR datasheet(58/100 Pages) NXP

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Table 41. 12-bit ADC characteristics (2.7 V to 3 V) (VREFH = VDDA, VREFL = VSS) 1

Symbol

Description

Min.

Typ.2

Max.

Unit

Notes

VDDA

Supply voltage

2.7

—

IDDA_ADC

Supply current per ADC

—

0.6

—

SMPLTS

Sample Time

275

—

Refer to the

Reference

Manual

TUE4

Total unadjusted error

—

±4

±8

LSB5

6, 7, 8, 9

DNL

Differential non-linearity

—

±1.0

—

LSB5

6, 7, 8, 9

INL

Integral non-linearity

—

±2.0

—

LSB5

6, 7, 8, 9

1. This table is not applicable to S32K14xW.

2. Typical values assume VDDA = 3 V, Temp = 25 °C, fADCK = 40 MHz, RAS=20 Ω, and CAS=10 nF.

3. The ADC supply current depends on the ADC conversion rate.

4. Represents total static error, which includes offset and full scale error.

5. 1 LSB = (VREFH - VREFL)/2N

6. The specifications are with averaging and in standalone mode only. Performance may degrade depending upon device

use case scenario. When using ADC averaging, refer to the Reference Manual to determine the most appropriate settings

for AVGS.

7. For ADC signals adjacent to VDD/VSS or XTAL/EXTAL or high frequency switching pins, some degradation in the ADC

performance may be observed.

8. All values guarantee the performance of the ADC for multiple ADC input channel pins. When using ADC to monitor the

internal analog parameters, assume minor degradation.

9. All the parameters in the table are given assuming system clock as the clocking source for ADC.

Table 42. 12-bit ADC characteristics (3 V to 5.5 V)(VREFH = VDDA, VREFL = VSS)

Symbol

Description

Min.

Typ.1

Max.

Unit

Notes

S32K1xx

S32K14xW

S32K1xx/

S32K14xW

S32K1xx/

S32K14xW

VDDA

Supply voltage

3.13

—

5.5

IDDA_ADC Supply current per ADC

—

SMPLTS Sample Time

275

—

Refer to the

Reference

Manual

TUE3

Total unadjusted error

—

±4

±8

LSB4

5, 6, 7, 8

DNL

Differential non-linearity

—

±0.7

—

LSB4

5, 6, 7, 8

INL

Integral non-linearity

—

±1.0

—

LSB4

5, 6, 7, 8

1. Typical values assume VDDA = 5.0 V, Temp = 25 °C, fADCK = 40 MHz, RAS=20 Ω, and CAS=10 nF unless otherwise stated.

2. The ADC supply current depends on the ADC conversion rate.

3. Represents total static error, which includes offset and full scale error.

4. 1 LSB = (VREFH - VREFL)/2N

5. The specifications are with averaging and in standalone mode only. Performance may degrade depending upon device

use case scenario. When using ADC averaging, refer to the Reference Manual to determine the most appropriate settings

for AVGS.

6. For ADC signals adjacent to VDD/VSS or XTAL/EXTAL or high frequency switching pins, some degradation in the ADC

performance may be observed.

7. All values guarantee the performance of the ADC for multiple ADC input channel pins. When using ADC to monitor the

internal analog parameters, assume minor degradation.

8. All the parameters in the table are given assuming system clock as the clocking source for ADC.

ADC electrical specifications

S32K1xx Data Sheet, Rev. 12, 02/2020

NXP Semiconductors

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