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M1E2G8SPI80-LX-R датащи(PDF) 2 Page - Silicom Ltd. |
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M1E2G8SPI80-LX-R датащи(HTML) 2 Page - Silicom Ltd. |
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2 / 5 page ![]() Silicom Ltd. Connectivity Solutions Page 2 Performance Features: Supports Intel I/O ® Acceleration Technology v3.0. Stateless offloads ( header split, RSS) Direct Cache access UDP, TCP, and IP Checksum offload UDP and TCP transmit checksum offload SCTP receive and transmit checksum offload Virtualization Ready: 8 Transmit and Receive queues per port Support up to 8 VMs per port ( 1 queue allocated to each VM) Packet interrupt coalescing timers (packet timers) and absolute- delay interrupt timers for both transmit and receive operation Common Key features: PCI Express ExpressModule Electromechanical Specification Revision 1.0 PCI Express Base Specification 2.0 (5 GTs) High performance, reliability, and low power use in Intel 82580 Quad integrated MAC + PHY and SERDES chip Controllers Hardware acceleration that can offload tasks from the host processor. The Controllers can offload TCP/UDP/IP checksum calculations and TCP segmentation Server class reliability, availability and performance features Link Aggregation and Load Balancing Switch dependent: 802.3ad (LACP), Generic Trunking ( GEC / FEC) Switch and NIC Independent Failover Priority queuing – 802.1p layer 2 priority encoding Virtual LANs –802.1q VLAN tagging Jumbo Frame (9.5KB) 802.x flow control Multicast/ broadcast Packet replication on receive Statistics for SNMP MIB II, Ethernet like MIB, and Ethernet MIB (802.3z, Clause 30) Supports Vital Product Data (VPD) Supports End to End CRC (ECRC) Supports Latency Tolerance Reporting (LTR) LEDs indicators for link/Activity status Hot Plug not supported. Can be supported by assembly change |
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