SB710 datasheet(38/88 Pages) AMD

38 / 88 page

AMD SB710 Databook

45215 Rev. 1.60 November 09

Signal Description

Pin Name

Type

Voltage

Functional Description

WAKE#/

GEVENT8#

I/O

S5_3.3V

PCI Express Wake /General Event 8

PCI Express Wake: WAKE# signal is required for PCI-E devices.

The PCI-E interface is off the NB, but the ACPI WAKE# is controlled

by SB. This signal is routed from the PCI-E device/slot to the SB.

Note: the WAKE# is in S5 domain so it is active when the system is

in S5 state. Care must be taken when plugging-in in the PCI-E

devices: the system should be transitioned in to G3 state (S5 Power

OFF) before a PCI-E device is installed. Plugging in a PCI-E device

when the system is in S5 state may cause the system to wake up.

That is because the WAKE# signal driven by the PCI-E device may

transition momentarily to active state when the device is installed

but has not been initialized to drive the signal in inactive state.

(Note: Hot plugging of PCI-E devices is not supported in the PC

architecture as, given the physical design of the interface, power will

be interrupted during installation.)

SLP_S2/GPM9#

I/O

S5_3.3V

S2 Sleep control: Assertion of SLP_S2 shuts off clocks when

system transitions to S2 state, and it takes place sometime after

CPU_STP# is asserted.

De-assertion of SLP_S2 turns on clocks when system transition

from S2 back to S0, and it takes place sometime after a wake-up

event

has been triggered.

ALLOW_LDTSTP

I/OD

0.8-V

threshold,

S5_3.3V

domain

ALLOW_LDTSTP: It is an input from NB to allow assertion of

LDT_STP#. When ALLOW_LDTSTP is de-asserted, SB710 cannot

assert LDT_STP#. ALLOW_LDTSTP can be used to implement

stutter mode operation for the CPU. Starting with RS78x, NB will

control the LDT_STP# during C state. In this configuration, SB can

drive ALLOW_LDTSTP to inform NB when it can assert LDT_STP#.

NB_PWRGD

3.3 V

Northbridge Power good

7.13

SMBus Interface / General Purpose Open Collector

Pin Name

Type

Voltage

Functional Description

SCL0/GPOC0#

I/OD

3.3 V (5-V Tolerance)

SMBus Clock 0 / General Purpose Open Collector 0

Note: Pin type is I/O when the pin is configured as

GPIO.

SDA0/GPOC1#

I/OD

3.3 V (5-V Tolerance)

SMBus Data 0 / General Purpose Open Collector 1

Note: Pin type is I/O when the pin is configured as

GPIO.

SCL1/GPOC2#

I/OD

S5_3.3V (to support

ASF)

SMBus Clock 1 / General Purpose Open Collector 2

Note: Pin type is I/O when the pin is configured as

GPIO.

SDA1/GPOC3#

I/OD

S5_3.3V (to support

ASF)

SMBus Data 1 / General Purpose Open Collector 3

Note: Pin type is I/O when the pin is configured as

GPIO.

SCL2/IMC_GPIO11

I/OD

S5_3.3V (5-V Tolerance) SMBus Clock 2/IMC GPIO11

Note: Pin type is I/O when the pin is configured as

GPIO.

SDA2/IMC_GPIO12

I/OD

S5_3.3V (5-V Tolerance) SMBus Data 2/IMC GPIO12

Note: Pin type is I/O when the pin is configured as

GPIO.

SCL3/IMC_GPIO13

I/OD

0.8-V threshold,

S5_3.3V domain

SMBus Clock 3/IMC GPIO13

Note: Pin type is I/O when the pin is configured as

GPIO.

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