REV. 0

AD10226

–12–

allowing the maximum swing at the input. The ENCODE input

should be bypassed with a capacitor to ground to reduce noise.

This ensures that the internal bias voltage is centered on the

encode signal (Figure 3). For best dynamic performance, imped-

ances at ENCODE and

ENCODE should match.

Figure 4 shows another preferred method for clocking the AD10226.

The clock source (low jitter) is converted from single-ended to

differential using an RF transformer. The back-to-back Schottky

diodes across the transformer secondary limit clock excursions

into the AD10226 to approximately 0.8 V p-p differential. This

helps prevent the large voltage swings of the clock from feeding

through to the other portions of the AD9433, and limits the noise

presented to the ENCODE inputs. A crystal clock oscillator can

also be used to drive the RF transformer if an appropriate limiting

resistor (typically 100

Ω) is placed in the series with the primary.

100

0.1 F

AD10226

ENCODE

ENCODE

CLOCK

SOURCE

Figure 4. Double-Ended 50 Sine Encode Circuit

ENCODE Voltage Level Definition

The voltage level definitions for driving ENCODE and

ENCODE

in differential mode is shown in Figure 6.

ENCODE

ENCODE

0.1 F

ENCODE

ENCODE

Figure 5. Differential Input Levels

Analog Input

The analog input is a single-ended ac-coupled high performance

1:1 transformer with an input impedance of 50

Ω to 350 MHz.

The nominal full scale input is 1.87 V p-p.

Special care was taken in the design of the analog input section

of the AD10226 to prevent damage and corruption of data when

the input is overdriven.

SFDR Optimization

The SFDR MODE pin enables (SFDR MODE = 1) a proprietary

circuit that may improve the spurious-free dynamic range (SFDR)

performance of the AD10226. It is useful in applications where the

dynamic range of the system is limited by discrete spurious frequency

content caused by nonlinearities in the ADC transfer function.

Enabling this circuit will give the circuit a dynamic transfer function,

meaning that the voltage threshold between two adjacent output

codes may change from clock cycle to clock cycle. While improv-

ing spurious frequency content, this dynamic aspect of the transfer

function may be inappropriate for some time domain applications

of the converter. Connecting the SFDR Mode pin to ground will

disable this function. The Typical Performance Characteristics

section of the data sheet illustrates the improvement in the linearity

of the converter and its effect on spurious-free dynamic range.

Digital Outputs

The digital outputs are 3.3 V (2.7 V to 3.6 V) TTL/CMOS-

compatible for lower power consumption. The output data format

is selectable through the data format select (DFS) CMOS input.

DFS = 1 selects offset binary coding (Table III); DFS = 0 se-

lects Two’s Complement coding (Table IV).

Digital

Code

Range = 2 V p-p

Output

4095

+0.92

1111 1111 1111

••

•

••

•

2048

0

1000 0000 0000

2047

–0.00045

0111 1111 1111

••

•

••

•

0

–0.92

0000 0000 0000

Table IV. Two’s Complement Output Coding

Digital

Code

Range = 2 V p-p

Output

+2047

+0.92

0111 1111 1111

••

•

••

•

00

0000 0000 0000

–1

–0.00045

1111 1111 1111

••

•

••

•

–2048

–0.92

1000 0000 0000

Voltage Reference

A stable and accurate 2.5 V voltage reference is designed into the

Timing

The AD10226 provides latched data outputs, with 10 pipeline

the rising edge of the ENCODE command (see Figure 1). The

length of the output data lines and loads placed on them should

be minimized to reduce transients within the AD10226; these

transients can detract from the converter’s dynamic performance.

The minimum guaranteed conversion rate of the AD10226 is

10 MSPS. At internal clock rates below 10 MSPS, dynamic perfor-

mance may degrade. Therefore, input clock rates below 10 MHz

should be avoided.

GROUNDING AND DECOUPLING

Analog and Digital Grounding

Proper grounding is essential in any high-speed, high resolution

system. Multilayer printed circuit boards (PCBs) are recommended

to provide optimal grounding and power schemes. The use of

ground and power planes offers distinct advantages:

1. The minimization of the loop area encompassed by a signal

and its return path.

2. The minimization of the impedance associated with ground

and power paths.

3. The inherent distributed capacitor formed by the powerplane,

PCB insulation, and ground plane.