MCP1633 datasheet(14/31 Pages) MICROCHIP

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MCP1633

DS20006289A-page 14

 2020 Microchip Technology Inc.

3.8

Current Sense Operational

Amplifier Negative Input (ISN)

This pin is directly connected to the inverting input of

the current sense operational amplifier.

3.9

Current Sense Offset (CSO)

This pin helps users to better set a peak current limit to

protect the application. Internally this pin is connected

to current source (20 µA typical). By connecting a

resistor between this pin and ground, the resistor

generates a DC level that is added over current sense

signal.

3.10

Current Sense Input (CS)

This is the input for the switch current used for Peak

Current Mode control. A blanking period of 30 ns

(typical) for CS signal is provided to avoid leading edge

spikes that can cause false PWM reset. The normal

PWM duty cycle will be terminated when the voltage on

the CS pin including the slope compensation ramp and

DC offset (CSO) is equal to the output of the error

amplifier. For Current Mode operation, the CS pin will

control the PWM output on a cycle-by-cycle basis. To

avoid the instability of the Peak Current Mode control

when the duty cycle is higher than 50%, a slope

compensation ramp generator is internally provided.

This circuit will add to the CS signal an artificially

generated ramp to avoid sub-harmonic oscillations.

The amplitude of the slope compensation ramp is

adjustable with one external resistor. If this pin is left

open, the PWM Controller will operate in Voltage Mode

Control. In this mode, the external switching MOSFET

transistor is not protected against overcurrent

conditions. Certain limitations related to the stability of

the closed-loop system must be taken into account by

the designer when the part operates in Voltage Mode

Control.

3.11

PWM Output Signal (VEXT)

VEXT is the internal MOSFET driver output pin, used to

drive the external transistor.

Connect to gate of external main switching N-channel

MOSFET.

3.12

Input Bias (VCC)

VCC is the input voltage pin. Connect the input voltage

source to the VCC pin. For normal operation, the

voltage on the VCC pin should range from +3.0V to

+5.5V. A bypass capacitor of at least 1 µF should be

connected between the VCC pin and the GND pin. This

decoupling capacitor must be located as close as

possible to the controller package.

3.13

Series Dimming MOSFET Gate

Driver Output (SDRV)

Series dimming N-channel MOSFET gate driver

output. Connect to gate of external N-channel

MOSFET to implement series FET PWM dimming and

fault disconnect.

3.14

PWM Dimming Input (DIMM)

External PWM dimming input. A direct PWM dimming

command can be applied to control the LED current

duty cycle and frequency. This PWM generates a

signal that controls the VEXT and SDRV outputs.

Setting this pin to logic level low, turns off switching,

disconnects the COMP pin, and sets SDRV to “0”. Con-

nect to VCC via 100 kΩ resistor when not used for PWM

dimming.

3.15

Overvoltage Protection Input

(OVP)

Output voltage input. Connect a resistor divider from

output voltage to GND to set output overvoltage

protection. The OVP circuits turns off the MOSFET

driver (VEXT pin set to “0”) and the series dimming

MOSFET driver (SDRV pin set to “0”) when the output

voltage reaches the OVP threshold.

3.16

Enable or External

Synchronization Input (EN/Sync)

When this pin is connected to GND (logic “0”) for more

than 100 µS (typical) the controller will go to DISABLE

state. A logic “1” enables the normal operation of the

MCP1633. When the device is disabled, the VEXT

output is set. This pin can also accept an external

signal for synchronization from an external clock

source. The user must provide a correct timing signal

for synchronization to ensure consistent operation of

PWM controller.

3.17

Exposed Thermal Pad (AGND)

Analog ground and power ground are both connected

here. This PAD must be connected to PCB ground

plane using multiple vias for good functionality.

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