PFS154 datasheet(33/91 Pages) PADAUK

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PFS154

8bit MTP Type IO Controller

Page 33 of 91

PDK-DS-PFS154_CN_V105 –Jun. 9, 2020

5.5. 16-bit Timer (Timer16)

PFS154 provide a 16-bit hardware timer (Timer16/T16) and its clock source may come from system clock

(CLK), internal high RC oscillator (IHRC), internal low RC oscillator (ILRC) , external crystal oscillator (EOSC),

PA0 or PA4. Before sending clock to the 16-bit counter, a pre-scaling logic with divided-by-1, 4, 16 or 64 is

selectable for wide range counting. The 16-bit counter performs up-counting operation only, the counter initial

values can be stored from data memory by issuing the stt16 instruction and the counting values can be loaded

to data memory by issuing the ldt16 instruction. The interrupt request from Timer16 will be triggered by the

selected bit which comes from bit[15:8] of this 16-bit counter, rising edge or falling edge can be optional chosen

by register integs.4. The hardware diagram of Timer16 is shown as Fig. 4.

Fig. 4: Hardware diagram of Timer16

There are three parameters to define the Timer16 using; 1

st parameter is used to define the clock source of

Timer16, 2

nd parameter is used to define the pre-scalar and the 3rd one is to define the interrupt source.

T16M

IO_RW

0x06

$ 7~5:

STOP, SYSCLK, X, PA4_F, IHRC, EOSC, ILRC, PA0_F

// 1

st par.

$ 4~3:

/1, /4, /16, /64

// 2

nd par.

$ 2~0:

BIT8, BIT9, BIT10, BIT11, BIT12, BIT13, BIT14, BIT15

// 3

rd par.

User can choose the proper parameters of T16M to meet system requirement, examples as below:

T16M

SYSCLK, /64, BIT15;

// choose (SYSCLK/64) as clock source, every 2^16 clock to set INTRQ.2=1

// if system clock SYSCLK = IHRC / 2 = 8 MHz

// SYSCLK/64 = 8 MHz/64 = 8 uS, about every 524 mS to generate INTRQ.2=1

T16M

PA0, /1, BIT8;

// choose PA0 as clock source, every 2^9 to generate INTRQ.2=1

// receiving every 512 times PA0 to generate INTRQ.2=1

T16M

STOP;

// stop Timer16 counting

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