OPA863 datasheet(13/24 Pages) TI

13 / 24 page

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(I=T .) F

F 85

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1 =

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5* 45* + 84'(

600Ÿ

12kŸ

RSH

1.65V

GND

Switchi ng

Circuit

ISH

VOUT

3.3V

OPA x863

250Ÿ

ADS705 6

3.3V

TLV320 1

VTH

MCU

Interrupt

Digital I/O

300V

3.3V

220pF

OPA2863

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SBOS982A – JUNE 2020 – REVISED JUNE 2020

Product Folder Links: OPA2863

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9.2 Low-Side Current Sensing

Power converters use current-mode feedback control for superior transient response and multi-phase load

sharing. Inverter stages control the phase currents for torque control in motor drives. Due to its simplicity and

low-cost, many of these topologies use difference amplifier based low-side current sensing. Figure 10 shows the

use of OPAx863 in a difference amplifier circuit for low-side current sensing.

Figure 10. Low-Side Current Sensing in Power Converters

9.2.1 Design Requirements

Table 1. Design Requirements

PARAMETER

DESIGN REQUIREMENT

Shunt resistor

10 mΩ

Input current

15 APP

Output voltage

3 VPP

Switching frequency

50 kHz

Data acquisition

1 MSPS with 0.1% accuracy

Input voltage due to ground bounce

10 Vpk

In a difference amplifier circuit, the output voltage is given by,

For lowest system noise, small values of RF and RG are preferred. The smallest value of RG is limited by the

input transient voltage (10V here) seen by the circuit, and is given by,

Where,

•

VIN(maximum) is the maximum input transient voltage seen by the circuit

•

VD is the forward voltage drop of ESD diodes at the amplifier input

•

ID(maximum) is the maximum current rating of the ESD diodes at the amplifier input

For a difference amplifier gain of 20 V/V, RF and RG of 12kΩ and 600Ω are used, respectively. With a clock

frequency of 40 MHz and ADS7056 sampling at 1 MSPS, the available acquisition time for amplifier output

settling is 550 ns. Figure 11 shows the simulation results for the circuit in Figure 10. The worst-case peak-to-

peak input transient condition is simulated. The OPAx863 devices output settles to within 0.1% accuracy within

543 ns. If use of a slower clock frequency with the ADC is desired, the acquisition time reduces for the same

sampling rate which worsens measurement accuracy. Alternatively, the sampling rate may be reduced to recover

the required acquisition time and 0.1% accuracy.

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