LP5009 datasheet(20/51 Pages) TI

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8.5.1.3 Transferring Data

Every byte put on the SDA line must be eight bits long, with the most-significant bit (MSB) being transferred first.

Each byte of data must be followed by an acknowledge bit. The acknowledge-related clock pulse is generated

by the master. The master releases the SDA line (HIGH) during the acknowledge clock pulse. The device pulls

down the SDA line during the ninth clock pulse, signifying an acknowledge. The device generates an

acknowledge after each byte has been received.

There is one exception to the acknowledge-after-every-byte rule. When the master is the receiver, it must

indicate to the transmitter an end of data by not acknowledging (negative acknowledge) the last byte clocked out

of the slave. This negative acknowledge still includes the acknowledge clock pulse (generated by the master),

but the SDA line is not pulled down.

After the START condition, the bus master sends a chip address. This address is seven bits long followed by an

eighth bit which is a data direction bit (READ or WRITE). For the eighth bit, a 0 indicates a WRITE, and a 1

indicates a READ. The second byte selects the register to which the data is written. The third byte contains data

to write to the selected register.

Data O utp ut

by Tran smitte r

Data O utp ut

by Tran smitte r

SCL Fr om

Master

Start

Condition

Clock Pulse fo r

Acknowledgment

ACK

NACK

Figure 8-10. Acknowledge and Not Acknowledge on I2C Bus

8.5.1.4 I2C Slave Addressing

The device slave address is defined by connecting GND or VCC to the ADDR0 and ADDR1 pins. A total of four

independent slave addresses can be realized by combinations when GND or VCC is connected to the ADDR0

and ADDR1 pins (see Table 8-2 and Table 8-3).

The device responds to a broadcast slave address regardless of the setting of the ADDR0 and ADDR1 pins.

Global writes to the broadcast address can be used for configuring all devices simultaneously. The device

supports global read using a broadcast address; however, the data read is only valid if all devices on the I2C bus

contain the same value in the addressed register.

LP5009, LP5012

SLVSEH2B – MAY 2019 – REVISED AUGUST 2020

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