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August 2004

ASM5P23S04A

rev 2.0

3.3

‘SpreadTrak’ Zero Delay Buffer

2

of 13

Notice: The information in this document is subject to change without notice.

ASM5P23S04A Configurations

Device

Feedback From

Bank A Frequency

Bank B Frequency

ASM5P23S04A-1

Bank A or Bank B

Reference

Reference

ASM5P23S04A-1H

Bank A or Bank B

Reference

Reference

ASM5P23S04A-2

Bank A

Reference

Reference /2

ASM5P23S04A-2

Bank B

2 X Reference

Reference

ASM5P23S04A-5H

Bank A or Bank B

Reference /2

Reference /2

‘SpreadTrak’

Many systems being designed now utilize a

technology

called

Spread

Frequency

Timing

Generation. ASM3P23S04A is designed so as not

to filter off the Spread Spectrum feature of the

Reference input, assuming it exists. When a zero

delay buffer is not designed to pass the Spread

Spectrum feature through, the result is a significant

amount

of

tracking

skew

which

may

cause

problems in the systems requiring synchronization.

Zero Delay and Skew Control

For applications requiring zero input-output delay, all outputs must be equally loaded.

-30

-25

-20

-15

-10

-5

0

5

10

15

20

25

30

0

-500

-1000

-1500

500

1000

1500

Output Load Difference: FBK Load - CLKA/CLKB Load (pF)

REF Input to CLKA/CLKB Delay Vs Difference in Loading between FBK pin and CLKA/CLKB pins