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SN74LVC2T45 датащи(PDF) 13 Page - Texas Instruments |
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SN74LVC2T45 датащи(HTML) 13 Page - Texas Instruments |
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13 / 32 page ![]() B1 DIR 5 7 A1 2 VCCA VCCB B2 6 A2 3 13 SN74LVC2T45 www.ti.com SCES516K – DECEMBER 2003 – REVISED JUNE 2017 Product Folder Links: SN74LVC2T45 Submit Documentation Feedback Copyright © 2003–2017, Texas Instruments Incorporated 8 Detailed Description 8.1 Overview The SN74LVC2T45 is dual-bit, dual-supply noninverting voltage level translation. Pin Ax and direction control pin are support by VCCA and pin Bx are support by VCCB. The A port is able to accept I/O voltages ranging from 1.65 V to 5.5 V, while the B port can accept I/O voltages from 1.65 V to 5.5 V. The high on DIR allows data transmission from A to B and a low on DIR allows data transmission from B to A. 8.2 Functional Block Diagram Figure 18. Logic Diagram (Positive Logic) 8.3 Feature Description 8.3.1 Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.65-V to 5.5-V Power-Supply Range Both VCCA and VCCB can be supplied at any voltage between 1.65 V and 5.5 V making the device suitable for translating between any of the voltage nodes (1.8-V, 2.5-V, 3.3-V and 5-V). 8.3.2 Support High-Speed Translation SN74LVC2T45 can support high data rate application. The translated signal data rate can be up to 420 Mbps when signal is translated from 3.3 V to 5 V. 8.3.3 Ioff Supports Partial-Power-Down Mode Operation Ioff will prevent backflow current by disabling I/O output circuits when device is in partial-power-down mode. 8.4 Device Functional Modes Table 1 lists the functional modes of the SN74LVC2T45 device. (1) Input circuits of the data I/Os always are active. Table 1. Function Table(1) (Each Transceiver) INPUT DIR OPERATION L B data to A bus H A data to B bus |
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