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FT232R USB UART IC Datasheet

Version 2.16

Document No.: FT_000053 Clearance No.: FTDI# 38

applications can be used to maintain product licensing this way. An application note, AN232R-02,

available from FTDI website (www.ftdichip.com) describes this feature.

The FT232R is capable of operating at a voltage supply between +3.3V and +5V with a nominal

operational mode current of 15mA and a nominal USB suspend mode current of 70µA. This allows greater

margin for peripheral designs to meet the USB suspend mode current limit of 2.5mA. An integrated level

converter within the UART interface allows the FT232R to interface to UART logic running at +1.8V, 2.5V,

+3.3V or +5V.

4.2 Functional Block Descriptions

The following paragraphs detail each function within the FT232R. Please refer to the block diagram shown

in Figure 2.1.

Internal EEPROM. The internal EEPROM in the FT232R is used to store USB Vendor ID (VID), Product ID

(PID), device serial number, product description string and various other USB configuration descriptors.

The internal EEPROM is also used to configure the CBUS pin functions. The FT232R is supplied with the

internal EEPROM pre-programmed as described in Section 8. A user area of the internal EEPROM is

available to system designers to allow storing additional data. The internal EEPROM descriptors can be

programmed in circuit, over USB without any additional voltage requirement. It can be programmed

using the FTDI utility software called FT_PROG, which can be downloaded from FTDI Utilities on the FTDI

website (www.ftdichip.com).

+3.3V LDO Regulator. The +3.3V LDO regulator generates the +3.3V reference voltage for driving the

USB transceiver cell output buffers. It requires an external decoupling capacitor to be attached to the

3V3OUT regulator output pin. It also provides +3.3V power to the 1.5kΩ internal pull up resistor on

USBDP. The main function of the LDO is to power the USB Transceiver and the Reset Generator Cells

rather than to power external logic. However, it can be used to supply external circuitry requiring a

+3.3V nominal supply with a maximum current of 50mA.

USB Transceiver. The USB Transceiver Cell provides the USB 1.1 / USB 2.0 full-speed physical interface

to the USB cable. The output drivers provide +3.3V level slew rate control signalling, whilst a differential

input receiver and two single ended input receivers provide USB data in, Single-Ended-0 (SE0) and USB

reset detection conditions respectfully. This function also incorporates the internal USB series termination

resistors on the USB data lines and a 1.5kΩ pull up resistor on USBDP.

USB DPLL. The USB DPLL cell locks on to the incoming NRZI USB data and generates recovered clock

and data signals for the Serial Interface Engine (SIE) block.

Internal 12MHz Oscillator - The Internal 12MHz Oscillator cell generates a 12MHz reference clock. This

provides an input to the x4 Clock Multiplier function. The 12MHz Oscillator is also used as the reference

clock for the SIE, USB Protocol Engine and UART FIFO controller blocks.

Clock Multiplier / Divider. The Clock Multiplier / Divider takes the 12MHz input from the Internal

Oscillator function and generates the 48MHz, 24MHz, 12MHz and 6MHz reference clock signals. The 48Mz

clock reference is used by the USB DPLL and the Baud Rate Generator blocks.

Serial Interface Engine (SIE). The Serial Interface Engine (SIE) block performs the parallel to serial

and serial to parallel conversion of the USB data. In accordance with the USB 2.0 specification, it

performs bit stuffing/un-stuffing and CRC5/CRC16 generation. It also checks the CRC on the USB data

stream.

USB Protocol Engine. The USB Protocol Engine manages the data stream from the device USB control

endpoint. It handles the low level USB protocol requests generated by the USB host controller and the

commands for controlling the functional parameters of the UART in accordance with the USB 2.0

specification chapter 9.

FIFO RX Buffer (128 bytes). Data sent from the USB host controller to the UART via the USB data OUT

endpoint is stored in the FIFO RX (receive) buffer. Data is removed from the buffer to the UART transmit

register under control of the UART FIFO controller. (Rx relative to the USB interface).