PIC16F917ESLASHML301 datasheet(29/272 Pages) MICROCHIP

29 / 272 page

Preliminary

DS41250E-page 27

PIC16F917/916/914/913

2.2.2.7

PIR2 Register

The PIR2 register contains the interrupt flag bits, as

shown in Register 2-7.

PIR2 – PERIPHERAL INTERRUPT REQUEST REGISTER 2 (ADDRESS: 0Dh)

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the global

enable

bit,

GIE

(INTCON<7>).

User

software should ensure the appropriate

interrupt flag bits are clear prior to enabling

an interrupt.

R/W-0

R-0

U-0

R/W-0

U-0

R/W-0

OSFIF

C2IF

C1IF

LCDIF

—LVDIF

—

CCP2IF

bit 7

bit 0

bit 7

OSFIF: Oscillator Fail Interrupt Flag bit

= System oscillator failed, clock input has changed to INTOSC (must be cleared in software)

= System clock operating

bit 6

C2IF: Comparator 2 Interrupt Flag bit

= Comparator output (C2OUT bit) has changed (must be cleared in software)

= Comparator output (C2OUT bit) has not changed

bit 5

C1IF: Comparator 1 Interrupt Flag bit

= Comparator output (C1OUT bit) has changed (must be cleared in software)

= Comparator output (C1OUT bit) has not changed

bit 4

LCDIF: LCD Module Interrupt bit

= LCD has generated an interrupt

= LCD has not generated an interrupt

bit 3

Unimplemented: Read as ‘0’

bit 2

LVDIF: Low Voltage Detect Interrupt Flag bit

= LVD has generated an interrupt

= LVD has not generated an interrupt

bit 1

Unimplemented: Read as ‘0’

bit 0

CCP2IF: CCP2 Interrupt Flag bit (only available in 16F914/917)

Capture Mode

= A TMR1 register capture occurred (must be cleared in software)

= No TMR1 register capture occurred

Compare Mode

= A TMR1 register compare match occurred (must be cleared in software)

= No TMR1 register compare match occurred

PWM mode

Unused in this mode

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

- n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

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