8 Detailed Description

8.1 Overview

Logic Diagram (Positive Logic) for the SN74HCS596 describes the SN74HCS596, an 8-bit shift register that

feeds an 8-bit D-type storage register. Both the shift register clock (SRCLK) and storage register clock (RCLK)

are positive-edge triggered. If both clocks are connected together, the shift register always is one clock pulse

ahead of the storage register. All inputs include Schmitt-triggers allowing for slow input transitions and providing

8.2 Functional Block Diagram

RCL K

OE

SRCLR

SRCLK

SER

13

12

10

11

14

D

R

15

1

Q

D

R

Q

D

Q

D

Q

2

3

4

5

6

D

R

7

9

Q

D

Q

Figure 8-1. Logic Diagram (Positive Logic) for SN74HCS596

8.3 Feature Description

8.3.1 Balanced CMOS Push-Pull Outputs

This device includes balanced CMOS push-pull outputs. The term "balanced" indicates that the device can sink

and source similar currents. The drive capability of this device may create fast edges into light loads so routing

and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable

of driving larger currents than the device can sustain without being damaged. It is important for the output power

of the device to be limited to avoid damage due to overcurrent. The electrical and thermal limits defined in the

Absolute Maximum Ratings must be followed at all times.

Unused push-pull CMOS outputs should be left disconnected.

8.3.2 Open-Drain CMOS Outputs

This device includes open-drain CMOS outputs. Open-drain outputs can only drive the output low. When in the

high logical state, open-drain outputs will be in a high-impedance state. The drive capability of this device may

create fast edges into light loads so routing and load conditions should be considered to prevent ringing.

SN74HCS596

SCLS840 – AUGUST 2020

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