SN74HCS264 datasheet(13/23 Pages) TI

номер детали	SN74HCS264

подробное описание детали	SN74HCS264 8-Bit Parallel-Out Serial Shift Registers With Schmitt-Trigger Inputs and Inverted Outputs

PDF	23 Pages

Scroll/Zoom	100%

производитель	TI [Texas Instruments]

домашняя страница	http://www.ti.com

Logo

13 / 23 page

9.2.2 Detailed Design Procedure

1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the

device and electrically close to both the VCC and GND pins. An example layout is shown in the Layout

section.

2. Ensure the capacitive load at the output is ≤ 50 pF. This is not a hard limit, however it will ensure optimal

performance. This can be accomplished by providing short, appropriately sized traces from the SN74HCS264

to the receiving device(s).

3. Ensure the resistive load at the output is larger than (VCC / IO(max)) Ω. This will ensure that the maximum

output current from the Absolute Maximum Ratings is not violated. Most CMOS inputs have a resistive load

measured in megaohms; much larger than the minimum calculated above.

4. Thermal issues are rarely a concern for logic gates, however the power consumption and thermal increase

can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd

Calculation.

9.2.3 Application Curve

CLK

CLR

Clear

Figure 9-2. Application timing diagram

www.ti.com

SN74HCS264

SCLS844 – AUGUST 2020

Submit Document Feedback

Product Folder Links: SN74HCS264

SN74HCS264 датащи(PDF) 13 Page - Texas Instruments