IS25LP064A-RHLA1 datasheet(10/99 Pages) ISSI

10 / 99 page

IS25LP064A/032A

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A

11/06/2015

For the device with dedicated RESET# function option on pin3/ball A4.

(pin1/ ball D4 will become HOLD# (IO3) pin, See the Ordering Information for the parts)

SYMBOL

TYPE

DESCRIPTION

CE#

INPUT

Same as the description in previous page

SI (IO0),

SO (IO1)

INPUT/OUTPUT

Same as the description in previous page

WP# (IO2)

INPUT/OUTPUT

Same as the description in previous page

HOLD# (IO3)

INPUT/OUTPUT

Hold/Serial Data IO (IO3):

When the QE bit of Status Register is set to “1”, HOLD#

pin is not available since it becomes IO3. When QE=0 the pin acts as HOLD#.

The HOLD# pin allows the device to be paused while it is selected. It pauses serial

communication by the master device without resetting the serial sequence. The

HOLD# pin is active low. When HOLD# is in a low state and CE# is low, the SO pin

will be at high impedance. Device operation can resume when HOLD# pin is brought

to a high state.

RESET#

INPUT/OUTPUT

RESET: Dedicated RESET# function is available only for specific parts. The

RESET# pin (or ball) will be independent of the QE bit of Status Register.

The RESET# is a hardware RESET signal. When RESET# is driven HIGH, the

memory is in the normal operating mode. When RESET# is driven LOW, the

memory enters reset mode and output is High-Z. If RESET# is driven LOW while an

internal WRITE, PROGRAM, or ERASE operation is in progress, data may be lost.

SCK

INPUT

Same as the description in previous page

Vcc

POWER

Same as the description in previous page

GND

GROUND

Same as the description in previous page

Unused

Same as the description in previous page

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