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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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IS25LP064A-RBLE1 датащи(PDF) 21 Page - Integrated Silicon Solution, Inc |
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IS25LP064A-RBLE1 датащи(HTML) 21 Page - Integrated Silicon Solution, Inc |
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21 / 99 page  IS25LP064A/032A Integrated Silicon Solution, Inc.- www.issi.com 21 Rev. A 11/06/2015 7. PROTECTION MODE The IS25LP064A/032A supports hardware and software write-protection mechanisms. 7.1 HARDWARE WRITE PROTECTION The Write Protection (WP#) pin provides a hardware write protection method for BP3, BP2, BP1, BP0, SRWD, and QE in the Status Register. Refer to the section 6.1 STATUS REGISTER. Write inhibit voltage (VWI) is specified in the section 9.8 POWER-UP AND POWER-DOWN. All write sequence will be ignored when Vcc drops to VWI. Table 7.1 Hardware Write Protection on Status Register SRWD WP# Status Register 0 Low Writable 1 Low Protected 0 High Writable 1 High Writable Note: Before the execution of any program, erase or write Status/Function Register instruction, the Write Enable Latch (WEL) bit must be enabled by executing a Write Enable (WREN) instruction. If the WEL bit is not enabled, the program, erase or write register instruction will be ignored. 7.2 SOFTWARE WRITE PROTECTION The IS25LP064A/032A also provides a software write protection feature. The Block Protection (TBS, BP3, BP2, BP1, BP0) bits allow part or the whole memory area to be write-protected. |
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