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AS7C3256A-8TCN датащи(PDF) 4 Page - Alliance Semiconductor Corporation

номер детали AS7C3256A-8TCN
подробное описание детали  3.3V 32K X 8 CMOS SRAM (Common I/O)
PDF  9 Pages
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производитель  ALSC [Alliance Semiconductor Corporation]
домашняя страница  https://www.alliancememory.com
Logo ALSC - Alliance Semiconductor Corporation

AS7C3256A-8TCN датащи(HTML) 4 Page - Alliance Semiconductor Corporation

  AS7C3256A-8TCN Datasheet HTML 1Page - Alliance Semiconductor Corporation AS7C3256A-8TCN Datasheet HTML 2Page - Alliance Semiconductor Corporation AS7C3256A-8TCN Datasheet HTML 3Page - Alliance Semiconductor Corporation AS7C3256A-8TCN Datasheet HTML 4Page - Alliance Semiconductor Corporation AS7C3256A-8TCN Datasheet HTML 5Page - Alliance Semiconductor Corporation AS7C3256A-8TCN Datasheet HTML 6Page - Alliance Semiconductor Corporation AS7C3256A-8TCN Datasheet HTML 7Page - Alliance Semiconductor Corporation AS7C3256A-8TCN Datasheet HTML 8Page - Alliance Semiconductor Corporation AS7C3256A-8TCN Datasheet HTML 9Page - Alliance Semiconductor Corporation  
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®
AS7C3256A-8
3/22/05; v.1.0
Alliance Semiconductor
P. 4 of 9
Read cycle (over the operating range)2,8
Key to switching waveforms
Read waveform 1 (address controlled)2,5,6,8
Read waveform 2 (CE controlled)2,5,7,8
Parameter
Symbol
-8
Unit
Notes
Min
Max
Read cycle time
tRC
8–
ns
Address access time
tAA
–
8
ns
2
Chip enable (CE) access time
tACE
–
8
ns
2
Output enable (OE) access time
tOE
–5
ns
Output hold from address change
tOH
3
–
ns
4
CE LOW to output in low Z
tCLZ
3
–
ns
3,4
CE HIGH to output in high Z
tCHZ
–
3
ns
3,4
OE LOW to output in low Z
tOLZ
0
–
ns
3,4
OE HIGH to output in high Z
tOHZ
–
3
ns
3,4
Power up time
tPU
0
–
ns
3,4
Power down time
tPD
–10
ns
3,4
Undefined output/don’t care
Falling input
Rising input
Address
Dout
Data valid
tOH
tAA
tRC
Supply
current
CE
OE
Dout
tRC1
tOE
tOLZ
tACE
tCHZ
tCLZ
tPU
tPD
ICC
ISB
50%
50%
tOHZ
Data valid



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