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WM8960CGEFL/V датащи(PDF) 17 Page - Cirrus Logic

номер детали WM8960CGEFL/V
подробное описание детали  Speaker and Headphone Drivers for Portable Audio Applications
PDF  94 Pages
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производитель  CIRRUS [Cirrus Logic]
домашняя страница  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

WM8960CGEFL/V датащи(HTML) 17 Page - Cirrus Logic

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WM8960
Rev 4.4
17
INTERNAL POWER ON RESET CIRCUIT
Power On Reset
Circuit
AVDD
INTERNAL PORB
VDD
GND
AGND
DCVDD
T
Figure 5 Internal Power on Reset Circuit Schematic
The WM8960 includes an internal Power-On-Reset Circuit, as shown in Figure 5, which is used to
reset the digital logic into a default state after power up. The POR circuit is powered from AVDD and
monitors DCVDD. It asserts PORB low if AVDD or DCVDD is below a minimum threshold.
DCVDD
AVDD
V
pord_on
DGND
AGND
Internal POR active
LO
HI
Device Ready
Internal
POR active
No Power
POR
Undefined
V
pora_off
V
pora
INTERNAL PORB
Figure 6 Typical Power up Sequence where AVDD is Powered before DCVDD
Figure 6 shows a typical power-up sequence where AVDD comes up first. When AVDD goes above
the minimum threshold, Vpora, there is enough voltage for the circuit to guarantee PORB is asserted
low and the chip is held in reset. In this condition, all writes to the control interface are ignored. Now
AVDD is at full supply level. Next DCVDD rises to Vpord_on and PORB is released high and all registers
are in their default state and writes to the control interface may take place.
On power down, where AVDD falls first, PORB is asserted low whenever AVDD drops below the
minimum threshold Vpora_off.



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