TS912AIYDT datasheet(7/21 Pages) STMICROELECTRONICS

7 / 21 page

TS912, TS912A, TS912B

Electrical characteristics

Doc ID 2325 Rev 7

7/21

Table 4.

VCC+ = 5 V, VCC- = 0 V, RL, CL connected to VCC/2, Tamb = 25 °C

(unless otherwise specified)

Symbol

Parameter

Min.

Typ.

Max.

Unit

Vio

Input offset voltage (Vic = Vo = VCC/2)

TS912

TS912A

TS912B

Tmin ≤ Tamb ≤ Tmax

TS912

TS912A

TS912B

ΔVio

Input offset voltage drift

μV/°C

Iio

Input offset current(1)

Tmin ≤ Tamb ≤ Tmax

100

200

Iib

Input bias current(1)

Tmin ≤ Tamb ≤ Tmax

150

300

ICC

Supply current (per amplifier, AVCL = 1, no load)

Tmin ≤ Tamb ≤ Tmax

230

350

450

μA

CMR

Common mode rejection ratio

Vic = 1.5 to 3.5 V, Vo = 2.5 V

SVR

Supply voltage rejection ratio (VCC+ = 3 to 5 V, Vo = VCC/2)

Avd

Large signal voltage gain (RL = 10 kΩ, Vo = 1.5 V to 3.5 V)

Tmin ≤ Tamb ≤ Tmax

V/mV

VOH

High level output voltage (Vid = 1 V)

RL = 100 kΩ

RL = 10 kΩ

RL = 600 Ω

RL = 100 Ω

Tmin ≤ Tamb ≤ Tmax

RL = 10 kΩ

RL = 600 Ω

4.95

4.9

4.25

4.8

4.1

4.95

4.55

3.7

VOL

Low level output voltage (Vid = -1 V)

RL = 100 kΩ

RL = 10 kΩ

RL = 600 Ω

RL = 100 Ω

Tmin ≤ Tamb ≤ Tmax

RL = 10 kΩ

RL = 600 Ω

350

1400

100

500

150

750

Output short-circuit current (Vid = ±1 V)

Source (Vo = VCC-)

Sink (Vo = VCC+)

GBP

Gain bandwidth product

(AVCL = 100, RL = 10 kΩ, CL = 100 pF, f = 100 kHz)

1MHz

SR+

Slew rate (AVCL = 1, RL = 10 kΩ, CL = 100 pF, Vi = 1 V to 4 V)

0.8

μs

SR-

Slew rate (AVCL = 1, RL = 10 kΩ, CL = 100 pF, Vi = 1 V to 4 V)

0.6

μs

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