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LP28303ASPF датащи(PDF) 6 Page - Lowpower Semiconductor inc |
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LP28303ASPF датащи(HTML) 6 Page - Lowpower Semiconductor inc |
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6 / 8 page ![]() LP28303A-00 Apr.-2017 Email: marketing@lowpowersemi.com www.lowpowersemi.com Page 6 of 8 Preliminary Datasheet LP28303A The resistor values of R1 and R2 are calculated by the following equations: For NTC Thermistors: ( ) ( ) ( ) ( ) ( ) For PTC Thermistors: ( ) ( ) ( ) ( ) ( ) K1(VNTC1)=45%, K2(VNTC2)=80%. Where RTL is the low temperature resistance and RTH is the high temperature resistance of thermistor, as specified by the thermistor manufacturer. R1 or R2 can be omitted if only one temperature (low or high) setting is required. Applying a voltage between the VNTC1 and VNTC2 thresholds to pin NTC disables the temperature-sensing feature. Layout Considerations Switch rise and fall times are kept under 5ns for maximum efficiency. To minimize radiation, the SW pin and input bypass capacitor leads (between VIN and GND) should be kept as short as possible. A ground plane should be used under the switching circuitry to prevent inter plane coupling. The Exposed Pad must be connected to the ground plane for proper power dissipation. The other paths contain only DC and/or 600KHz tri-wave ripple current and are less critical. With the exception of the input and output filter capacitors (which should be connected to GND) all other components that return to ground should be connected to GND. |
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