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AS7C252MNTF18A датащи(PDF) 1 Page - Alliance Semiconductor Corporation |
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AS7C252MNTF18A датащи(HTML) 1 Page - Alliance Semiconductor Corporation |
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1 / 18 page ![]() January 2005 Copyright © Alliance Semiconductor. All rights reserved. ® AS7C252MNTF18A 1/17/05, v 1.1 Alliance Semiconductor P. 1 of 18 2.5V 2M x 18 Flowthrough SRAM with NTDTM Features • Organization: 2,097,152 words × 18 bits •NTD™architecture for efficient bus operation • Fast clock to data access: 7.5/8.5/10 ns •Fast OE access time: 3.5/4.0 ns • Fully synchronous operation • Flow-through mode • Asynchronous output enable control • Available in 100-pin TQFP package • Byte write enables • Clock enable for operation hold • Multiple chip enables for easy expansion • 2.5V core power supply • Self-timed write cycles • Interleaved or linear burst modes • Snooze mode for standby operation Logic block diagram Selection guide -75 -85 -10 Units Minimum cycle time 8.5 10 12 ns Maximum clock access time 7.5 8.5 10 ns Maximum operating current 325 300 275 mA Maximum standby current 140 130 130 mA Maximum CMOS standby current (DC) 90 90 90 mA Address D Q CLK register Output buffer DQ [a,b] 20 20 CLK CE0 CE1 CE2 A[19:0] OE CEN Control CLK logic Data D Q CLK input register 18 18 OE 2M x 18 SRAM array R/W DQ [a,b] BWa BWb CLK Q D ADV / LD LBO burst logic addr. registers Write delay 20 ZZ CLK 18 18 18 18 |
Аналогичный номер детали - AS7C252MNTF18A |
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Аналогичное описание - AS7C252MNTF18A |
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