7

All data sheets are subject to change without notice

©2005 Maxwell Technologies

All rights reserved.

16-Bit Latchup Protected ADC

7805ALP

01.10.05 Rev 9

BUSY delay after data valid

t

10

9, 10, 11

50

200

--

ns

Previous data valid delay after R/C low

t

11

9, 10, 11

--

7.4

--

µ s

R/C to CS setup time

t

12

9, 10, 11

10

--

--

ns

Time between conversions

t

13

9, 10, 11

10

--

--

µ s

Bus access time

t

14

9, 10, 11

10

--

83

ns

1. Tested by application of signal.

CS

R/C

BUSY

1

X

X

None. Databus is in Hi-Z state.

0

1

Initiates conversion "n". Databus remains in Hi-Z state.

0

1

Initiates conversion "n". Databus enters Hi-Z state.

01

Conversion "n" completed. Valid data from conversion "n" on the databus.

1

1

Enables databus with valid data from conversion "n".

1

0

Enables databus with valid data from conversion "n-1". Conversion "n" in progress.

0

0

Enables databus with valid data from conversion "n-1". Conversion "n" in

progress."

00

New conversion initiated without acquisition of a new signal. Data will be invalid.

CS and/or R/C must be HIGH when BUSY goes HIGH.

X

X

0

New convert commands ignored. Conversion "n" in progress.

(V