2

SCD4435N Rev B

FIGURE 1 – TRANSMITTER LOGIC WAVEFORMS

FIGURE 2 – RECEIVER LOGIC WAVEFORMS

DATA IN

DATA IN

INHIBIT

LINE TO LINE

OUTPUT

Notes: 1. Data and DATA inputs must be complementry waveforms or 50% duty cycle average, with no delays between them, and in the same state during

the off time (both high and low).

2. Region 1 ; no output signal, High Z state, (Receive Mode), Region 2; No Output signal, Low Z state, (Terminate Mode), Region 3, Transmitter signal

on, low Z.

Region 1

2

3

Note overlap

devices, the receiver outputs are swapped as shown by the dashed lines

level

LINE TO LINE

INPUT

Rx DATA OUT

Rx DATA OUT

BLOCK DIAGRAM (WITHOUT TRANSFORMER)

SHAPING

OUTPUT

STAGE

COMP.

COMP.

ACTIVE

FILTER

INPUT

AMP

DRIVER

TX DATA IN

TX DATA IN

TX INHIBIT

+5 V

RX DATA IN

RX DATA IN

STROBE

TX DATA OUT

TX DATA OUT

RX DATA OUT

RX DATA OUT

-12V or -15V

EXT. THRESHOLD

DATA

SET INTERNAL

DATA

DATA

EXT. THRESHOLD

DATA

+15V or +12V

V+

V-

THRESHOLD