KSZ8893FQL datasheet(53/109 Pages) MICROCHIP

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KSZ8893FQL

DS00003038B-page 52

 2019 Microchip Technology Inc.

Aging Enable

R/W

1 = Enable age function in the chip

0 = Disable age function in the chip

Invert of

P2LED3 (pin 20)

value during

reset

Note: P2LED3

has internal pull-

down.

Fast Age Enable

R/W

1 = Turn on fast age (800 μs)

Aggressive Back-Off

Enable

R/W

1 = Enable more aggressive back off algorithm in half-

duplex mode to enhance performance. This is not an

IEEE standard.

Unicast Port-VLAN

Mismatch Discard

R/W

This feature is used with port-VLAN (described in reg.

17, reg. 33, etc.)

1 = All packets cannot cross VLAN boundary

0 = Unicast packets (excluding unknown/multicast/

broadcast) can cross VLAN boundary

Note: Port mirroring is not supported if this bit is set to

“0”.

Multicast Storm

Protection Disable

R/W

1 = Broadcast Storm Protection does not include

multicast packets. Only DA = FF-FF-FF-FF-FF-FF

packets will be regulated.

0 = Broadcast Storm Protection includes DA = FF-FF-

FF-FF-FF-FF and DA[40] = 1 packets.

Back Pressure Mode

R/W

1 = Carrier sense based back pressure is selected

0 = Collision based back pressure is selected

Flow Control and

Back Pressure Fair

Mode

R/W

1 = Fair mode is selected. In this mode, if a flow con-

trol port and a non-flow control port talk to the same

destination port, packets from the non-flow control

port may be dropped. This is to prevent the flow con-

trol port from being flow controlled for an extended

period of time.

0 = In this mode, if a flow control port and a non-flow

control port talk to the same destination port, the flow

control port will be flow controlled. This may not be

“fair” to the flow control port.

No Excessive

Collision Drop

R/W

1 = The switch will not drop packets when 16 or more

collisions occur.

0 = The switch will drop packets when 16 or more col-

lisions occur.

Huge Packet

Support

R/W

1 = Will accept packet sizes up to 1916 bytes (inclu-

sive). This bit setting will override setting from bit 1 of

this register.

0 = The max packet size will be determined by bit 1 of

this register.

Legal Maximum

Packet Size Check

Enable

R/W

0 = Will accept packet sizes up to 1536 bytes (inclu-

sive).

1 = 1522 bytes for tagged packets, 1518 bytes for

untagged packets. Any packets larger than the speci-

fied value will be dropped.

SMRXD0 (pin

85) value during

reset

TABLE 4-7:

GLOBAL REGISTERS (0-15) (CONTINUED)

Bit

Name

R/W

Description

Default

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