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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ADC3543 датащи(PDF) 34 Page - Texas Instruments |
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ADC3543 датащи(HTML) 34 Page - Texas Instruments |
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34 / 68 page  7.3.4.5.2 Serialized CMOS Interface In serialized CMOS mode, the ADC354x device supports complex decimation output Figure 7-34 and real decimation output Figure 7-35. The examples are shown for 16-bit output for 2-wire (8x serialization) and 1-wire (16x serialization). FCLK D12 D11 FCLK D11 2-Wire 8x Serialization 1-Wire 16x Serialization DCLK DCLK AQ <15:0> AI <15:0> AI D13 AI D11 AI D9 AI D7 AI D5 AI D3 AI D1 AI D12 AI D10 AI D8 AI D6 AI D4 AI D2 AI D0 AQ D13 AQ D11 AQ D9 AQ D7 AQ D5 AQ D3 AQ D12 AQ D10 AQ D8 AQ D6 AQ D4 AQ D2 AQ D1 AQ D0 AI D15 AI D14 AQ D15 AQ D14 Figure 7-34. Output Data Format in Complex Decimation Table 7-6 illustrates the output interface data rate along with the corresponding DCLK/DCLKIN and FCLK frequencies based on output resolution (R), number of serial CMOS lanes (L) and complex decimation setting (N). Furthermore the table shows an actual lane rate example for the 2- and 1- wire interface, 16-bit output resolution and complex decimation by 16. Table 7-6. Serial CMOS Lane Rate Examples with Complex Decimation and 16-bit Output Resolution DECIMATION SETTING ADC SAMPLING RATE OUTPUT RESOLUTION # of WIRES FCLK DCLKIN, DCLK DOUT N FS R L FS / N [DOUT] / 2 FS x 2 x R / L / N 16 65 MSPS 16 2 4.0625 MHz 32.5 MHz 65 MHz 1 65 MHz 130 MHz ADC3541 SBAS840 – JULY 2020 www.ti.com 34 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADC3541 |
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