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AS3900

Data Sheet - Detail ed Description

8.4.1 SDI Operation Mode Bits

In general there are 3 modes that can be selected by A7 and A6. A5 to A0 contains the register address of the selected register. D7 to D0 contain

one byte that can be written or read from the selected address. A Write and Read cycle can be covered with 2 bytes, a Command cycle within 1

byte operation. An Enable LOW pulse indicates the end of all possible modes.

Table 14. SDI Operation Patterns

Mode

Mode Pattern

Mode related Data

Mode

Register Address

Register Data

A7

A6

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

8.4.2 Writing of Data to Addressable Registers (WRITE Mode)

DATAI is sampled at the falling edge of SCLK as shown in the following diagrams. An Enable LOW pulse indicates the end of the WRITE

command after register has been written. The following example shows a write command.

Figure 14. Writing of a Single Byte (falling edge sampling)

Due to the limited range of the Register Address of 6 bits (A5 to A0), only the register 0x00 to 0x3F are directly addressable. All other registers

(0x3F to 0x51 in the MAIN register) can only be accessed via the auto-incrementing Write cycle. The auto-incrementing Write cycle can be

applied by remaining SEN to HIGH and providing further clock cycles on SCLK (falling edges).

Figure 15. Writing of Register Data with Auto-incrementing Address

Write Mode

0

0

xx

xx

xxx

xx

xx

xx

x

Read Mode

0

1

x

x

x

x

x

x

RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0

Spare Mode

1

0

Command Mode

1

1

C5

C4

C3

C2

C1

C0













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