ST8500 datasheet(11/37 Pages) STMICROELECTRONICS

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ST8500

Device architecture

2.2.6

General-purpose input/outputs (GPIOs)

The ST8500 device has 3 GPIOs ports named GPIO00, GPIO01 and GPIO03. Each port

can control 8 pins. Each GPIO pin can be individually configured by software as output

(push-pull or open drain, with or without pull-up or pull-down), as input (floating, with or

without pull-up or pull-down) or as peripheral alternate functions (with or without pull-up or

pull-down).

The GPIO03 port exports system defined functionalities such as boot mode selection and

JTAG that the running code can overwrite after the bootloader has left the control to it. The

final system design must take care of this special configuration.

External interrupt

Each GPIOs port can generate interrupts depending on a level (low and high), or a

transactional value of the pin (rising or falling edge). For each port, one interrupt line is

dedicated. The pins of one port share the same interrupt line.

2.2.7

General-purpose timer (GPT)

There are 4 general-purpose timers (GPT0 to GPT3) embedded in the ST8500.

GPTs have a 32-bit auto-reload up/downcounter and a 32-bit pre-scaler. The counters can

be frozen in debug mode.

The GPT0 timer is also connected to the zero crossing comparator so it is able to record the

timestamp of the ZC event.

2.2.8

Window Watchdog (WWDG)

The window watchdog is based on a 7-bit downcounter that can be set as free running. It

can be used as a watchdog to reset the device when a problem occurs. It is clocked from

the main clock. It has an early warning interrupt capability and the counter can be frozen in

debug mode.

2.2.9

SysTick timer

The Cortex™-M4F has a 24-bit system timer, SysTick, which counts down from the

programmable reload value to zero. It supports the auto-reload and can generate a

maskable system interrupt when the counter reaches zero.

2.2.10

Universal synchronous/asynchronous receiver transmitters (USART)

The ST8500 device has two embedded universal synchronous/asynchronous receiver

transmitters (USART0 to USART1) and one embedded universal asynchronous receiver

transmitter (USART2).

These interfaces provide asynchronous communication, IrDA SIR ENDEC support,

multiprocessor communication mode, single-wire half-duplex communication mode; they

have the LIN Master/Slave capability, Smart card mode (ISO 7816 compliant) and SPI-like

communication capability.

They provide hardware management of the CTS and RTS signals and the RS485 driver

enable. The maximum communication speed is up to 1 Mbit/s.

All USARTs have a clock domain (ICLK) independent from the Cortex™ clock (PCLK).

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