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Proprietary to OmniVision Technologies
Version 1.3, September 15, 2003
OV9625/OV9121
CMOS SXGA (1.3 MPixel) CAMERACHIP™
Omni
ision
11
CLKRC
00
RW
Clock Rate Control
Bit[7]:
Internal PLL ON/OFF selection
0:
PLL disabled
1:
PLL enabled
Bit[6]:
Digital video port master/slave selection
0:
Master mode, sensor provides PCLK
1:
Slave mode, external PCLK input from XCLK1 pin
Bit[5:0]:
Clock divider
CLK = XCLK1/(decimal value of CLKRC[5:0] + 1)
12
COMH
20
RW
Common Control H
Bit[7]:
SRST
1:
Initiates soft reset. All register are set to factory
default values after which the chip resumes normal
operation
Bit[6]:
Resolution selection
0:
SXGA
1:
VGA
Bit[5]:
Average luminance value pixel counter ON/OFF
0:
OFF
1:
ON
Bit[4]:
Reserved
Bit[3]:
Master/slave selection
0:
Master mode
1:
Slave mode
Bit[2]:
Window output selection
0:
Output only pixels defined by window registers
1:
Output all pixels
Bit[1]:
Color bar test pattern
0:
OFF
1:
ON
Bit[0]:
Reserved
Table 11
Device Control Register List
Address
(Hex)
Register
Name
Default
(Hex)
R/W
Description
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