PR533_SDS

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Product short data sheet

COMPANY PUBLIC

Rev. 3.6 — 27 October 2014

206436

27 of 36

NXP Semiconductors

PR533

USB NFC integrated reader solution

[1]

[2]

27.12 MHz quartz starts in less than 800

s. For example, quartz like TAS-3225A, TAS-7 or KSS2F with

appropriate layout.

[3]

The PR533 has an internal hold time of around 270 ns for the SDA signal to bridge the undefined region of

the falling edge of P50_SCL.

Fig 7.

Table 35.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

SCL clock frequency

0

-

400

kHz

hold time (repeated) START condi-

tion

after this period, the

first clock pulse is

generated

600

-

-

ns

set-up time for a repeated START

condition

600

-

-

ns

set-up time for STOP condition

600

-

-

ns

LOW period of the SCL clock

P50_SCL

1300 -

-

ns

HIGH period of the SCL clock

P50_SCL

600

-

-

ns

data hold time

0

-

900

ns

data set-up time

100

-

-

ns

rise time of both SDA and SCL sig-

nals

P50_SCL

[1] 20

-

300

ns

fall time of both SDA and SCL sig-

nals

P50_SCL

[1] 20

-

300

ns

bus free time between a STOP

and START condition

1.3

-

-

ms

stretch time

stretching time on

P50_SCL when

woken-up on its

own address

[2]

--

1

ms

hold time

internal for SDA

330

-

590

ns

internal for SDA in

SPD mode

[3]

-270

-ns

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SDA

SCL

SSr

P

S