LM4935 datasheet(21/112 Pages) NSC

21 / 112 page

12.0 Status & Control Registers (Continued)

12.1 BASIC CONFIGURATION REGISTER

This register is used to control the basic function of the chip.

TABLE 2. BASIC (0x00h)

Bits

Field

Description

1:0

CHIP_MODE

The LM4935 can be placed in one of four modes which dictate its basic operation. When a new

mode is selected the LM4935 will change operation silently and will re-configure the power

management profile automatically. The modes are described as follows:

CHIP MODE

Audio System

Detection System

Typical Application

Off

Power-down Mode

Off

Stand-by mode with headset event

detection

Off

Active without headset event detection

Active with headset event detection

PLL_ENABLE

If set the PLL can be used.

USE_OSC

If set the power management and control circuits will assume that no external clock is available and

will resort to using an on-chip oscillator for SAR, headset detection and analog power management

functions such as click and pop.

5:4

CAP_SIZE

Programs the extra delays required to stabilize once charge/discharge is complete, based on the size

of the bypass capacitor.

CAP_SIZE

Bypass Capacitor Size

Turn-off/on time

0.1 µF

45 ms/75 ms

1 µF

45 ms/140 ms

2.2 µF

45 ms/260 ms

4.7 µF

45 ms/500 ms

STEREO

If set, the mixers assume that the signals on the left and right internal busses are highly correlated

and when these signals are combined their levels are reduced by 6 dB to allow enough headroom for

them to be summed at the Loudspeaker, Earpiece, CPOUT, and AUXOUT amplifiers. For the

Headphone amplifier, if this bit is set, the left and right signal levels are routed to the corresponding

left or right headphone output; if this bit is cleared, the left and the right signals are added and routed

to both headphone outputs and their levels are reduced by 6dB to allow enough headroom.

OCL

If set the part is placed in OCL (Output Capacitor Less) mode.

For reliable headset / push button detection the following bits should be defined before enabling the headset detection system by

setting bit 0 of CHIP_MODE:

The OCL-bit (Cap / Capless headphone interface; bit 7 of this register)

The headset insert/removal debounce settings (bits 6:3 of DETECT (0x17h))

The BTN_TYPE-bit (Parallel / Series push button type; bit 3 MIC_2 register (0x0Ch))

The parallel push button debounce settings (bits 5:4 of MIC_2 register (0x0Ch))

All register fields controlling the audio system should be defined before setting bit 1 of CHIP_MODE and should not be altered

while the audio sub-system is active.

If the analog or digital levels are below −12 dB then it is not necessary to set the stereo bit allowing greater output levels to be

obtained for such signals.

LM4935 датащи(PDF) 21 Page - National Semiconductor (TI)

LM4935 датащи(HTML) 21 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL