AD5570ARS datasheet(21/24 Pages) AD

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AD5570

Rev. 0 | Page 21 of 24

AD5570 to MC68HC11 Interface

Figure 41 shows an example of a serial interface between the

AD5570 and the MC68HC11 microcontroller. The serial

peripheral interface (SPI) on the MC68HC11 is configured for

master mode (MSTR = 1), clock polarity bit (CPOL = 0), and

the clock phase bit (CPHA = 1). The SPI is configured by

writing to the SPI control register (SPCR)—see the 68HC11

User Manual. SCK of the 68HC11 drives the SCLK of the

AD5570, the MOSI output drives the serial data line (DIN) of

the AD5570, and the MISO input is driven from SDO. The

SYNC is driven from one of the port lines, in this case PC7.

When data is being transmitted to the AD5570, the SYNC line

(PC7) is taken low and data is transmitted MSB first. Data

appearing on the MOSI output is valid on the falling edge of

SCK. Eight falling clock edges occur in the transmit cycle, so, in

order to load the required 16-bit word, PC7 is not brought high

until the second 8-bit word has been transferred to the DAC’s

input shift register.

AD5570*

SCLK

DIN

SYNC

MOSI

SCLK

PC7

MC68HC11*

*ADDITIONAL PINS OMITTED FOR CLARITY

SDO

MISO

Figure 41. AD5570 to MC68HC11 Interface

LDAC is controlled by the PC6 port output. The DAC can be

updated after each 2-byte transfer by bringing LDAC low. This

example does not show other serial lines for the DAC. If CLR

were used, it could be controlled by port output PC5, for

example.

AD5570 to 8051 Interface

The AD5570 requires a clock synchronized to the serial data.

For this reason, the 8051 must be operated in Mode 0. In this

mode, serial data enters and exits through RxD, and a shift clock

is output on RxD.

P3.3 and P3.4 are bit programmable pins on the serial port and

are used to drive SYNC and LDAC, respectively.

The 8051 provides the LSB of its SBUF register as the first bit in

the data stream. The user must ensure that the data in the SBUF

first.

AD5570*

SCLK

DIN

SYNC

TxD

P3.3

8xC51*

*ADDITIONAL PINS OMITTED FOR CLARITY

SDO

RxD

VLOGIC

LDAC

P3.4

Figure 42. AD5570 to 8051 Interface

When data is to be transmitted to the DAC, P3.3 is taken low.

Data on RxD is clocked out of the microcontroller on the rising

edge of TxD and is valid on the falling edge. As a result, no glue

logic is required between this DAC and the microcontroller

interface.

The 8051 transmits data in 8-bit bytes with only eight falling

clock edges occurring in the transmit cycle. Because the DAC

expects a 16-bit word, SYNC (P3.3) must be left low after the

first eight bits are transferred. After the second byte has been

transferred, the P3.3 line is taken high. The DAC may be

updated using LDAC via P3.4 of the 8051.

AD5570 to ADSP2101/ADSP2103

An interface between the AD5570 and the ADSP2101/

ADSP2103 is shown in Figure 43. The ADSP2101/ADSP2103

should be set up to operate in the SPORT transmit alternate

framing mode. The ADSP2101/ADSP2103 are programmed

through the SPORT control register and should be configured

as follows: internal clock operation, active low framing, and

16-bit word length.

Transmission is initiated by writing a word to the Tx register

after the SPORT has been enabled. As the data is clocked out of

the DSP on the rising edge of SCLK, no glue logic is required to

interface the DSP to the DAC. In the interface shown, the DAC

output is updated using the LDAC pin via the DSP. Alterna-

tively, the LDAC input could be tied permanently low, and then

the update takes place automatically when TFS is taken high.

AD5570*

SCLK

DIN

SYNC

SCLK

RFS

ADSP2101/

ADSP2103*

*ADDITIONAL PINS OMITTED FOR CLARITY

SDO

TFS

LDAC

Figure 43. AD5570 to ADSP2101/ADSP2103 Interface

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