HD64F3694F datasheet(21/432 Pages) RENESAS

21 / 432 page

Rev. 4.00, 03/04, page xxi of xxviii

Section 12 Timer W

Figure 12.1 Timer W Block Diagram......................................................................................... 147

Figure 12.2 Free-Running Counter Operation ............................................................................ 157

Figure 12.3 Periodic Counter Operation..................................................................................... 158

Figure 12.4 0 and 1 Output Example (TOA = 0, TOB = 1)........................................................ 158

Figure 12.5 Toggle Output Example (TOA = 0, TOB = 1) ........................................................ 159

Figure 12.6 Toggle Output Example (TOA = 0, TOB = 1) ........................................................ 159

Figure 12.7 Input Capture Operating Example........................................................................... 160

Figure 12.8 Buffer Operation Example (Input Capture)............................................................. 160

Figure 12.9 PWM Mode Example (1) ........................................................................................ 161

Figure 12.10 PWM Mode Example (2) ...................................................................................... 162

Figure 12.11 Buffer Operation Example (Output Compare) ...................................................... 162

Figure 12.12 PWM Mode Example

(TOB, TOC, and TOD = 0: initial output values are set to 0)................................ 163

Figure 12.13 PWM Mode Example

(TOB, TOC, and TOD = 1: initial output values are set to 1)................................ 164

Figure 12.14 Count Timing for Internal Clock Source............................................................... 165

Figure 12.15 Count Timing for External Clock Source.............................................................. 165

Figure 12.16 Output Compare Output Timing ........................................................................... 166

Figure 12.17 Input Capture Input Signal Timing........................................................................ 166

Figure 12.18 Timing of Counter Clearing by Compare Match................................................... 167

Figure 12.19 Buffer Operation Timing (Compare Match).......................................................... 167

Figure 12.20 Buffer Operation Timing (Input Capture) ............................................................. 168

Figure 12.21 Timing of IMFA to IMFD Flag Setting at Compare Match .................................. 168

Figure 12.22 Timing of IMFA to IMFD Flag Setting at Input Capture...................................... 169

Figure 12.23 Timing of Status Flag Clearing by CPU................................................................ 169

Figure 12.24 Contention between TCNT Write and Clear ......................................................... 170

Figure 12.25 Internal Clock Switching and TCNT Operation.................................................... 171

Figure 12.26 When Compare Match and Bit Manipulation Instruction to TCRW

Occur at the Same Timing ..................................................................................... 172

Section 13 Watchdog Timer

Figure 13.1 Block Diagram of Watchdog Timer ........................................................................ 173

Figure 13.2 Watchdog Timer Operation Example...................................................................... 177

Section 14 Serial Communication Interface3 (SCI3)

Figure 14.1 Block Diagram of SCI3........................................................................................... 180

Figure 14.2 Data Format in Asynchronous Communication ...................................................... 195

Figure 14.3 Relationship between Output Clock and Transfer Data Phase

(Asynchronous Mode)(Example with 8-Bit Data, Parity, Two Stop Bits)............... 195

Figure 14.4 Sample SCI3 Initialization Flowchart ..................................................................... 196

Figure 14.5 Example SCI3 Operation in Transmission in Asynchronous Mode

(8-Bit Data, Parity, One Stop Bit)............................................................................ 197

Figure 14.6 Sample Serial Transmission Flowchart (Asynchronous Mode) .............................. 198

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