DMOS Microstepping Driver with Translator

A3979

9

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

cuitry uses a one-shot timer to control the duration of time

PWM control circuit, the CTx component sets the compara-

tor blanking time. This function blanks the output of the

current-sense comparators when the outputs are switched

by the internal current-control circuitry. The comparator

outputs are blanked to prevent false overcurrent detection

due to reverse recovery currents of the clamp diodes, or to

switching transients related to the capacitance of the load.

used to generate a gate supply greater than that of VBB for

driving the source-side DMOS gates. A 0.22 μF ceramic

capacitor should be connected between CP1 and CP2 for

pumping purposes. In addition, a 0.22 μF ceramic capacitor

is required between VCP and VBB, to act as a reservoir for

operating the high-side DMOS gates.

operate the sink-side DMOS outputs. The VREG pin must

internally monitored, and in the case of a fault condition, the

DMOS outputs of the device are disabled.

E

¯¯

N

¯¯

A

¯¯

B

¯¯

L

¯¯

E

enables all of the DMOS outputs. When set to a logic high,

the outputs are disabled. The inputs to the translator (STEP,

DIR, MS1, and MS2), all remain active, independent of the

¯E¯¯N¯¯A¯¯B¯¯L¯¯E¯ input state.

age on VCP, the outputs of the device are disabled until the

fault condition is removed.

lockout (UVLO) circuit disables the drivers and resets the

translator to the Home state.

S

¯¯

L

¯¯

E

¯¯

E

¯¯

P

is used to minimize power consumption when the motor is

not in use. It disables much of the internal circuitry includ-

ing the output DMOS FETs, current regulator, and charge

pump. Setting this to a logic high allows normal operation,

as well as start-up (at which time the A3979 drives the

motor to the Home microstep position). When bringing the

device out of Sleep mode, in order to allow the charge pump

(gate drive) to stabilize, provide a delay of 1 ms before issu-

ing a step command signal on the STEP input.

Percent Fast Decay Input (PFD).

When a STEP

input signal commands a lower output current than the

previous step, it switches the output current decay to either

Slow, Fast, or Mixed decay mode, depending on the voltage

level at the PFD input. If the voltage at the PFD input is

Fast decay mode is selected. Mixed decay mode is selected

the next section. This terminal should be decoupled with a

0.1 μF capacitor.

Mixed Decay Operation. If the voltage on the PFD input

in Mixed decay mode, as determined by the step sequence

(shown in figures 2 through 5). As the trip point is reached,

the device goes into Fast decay mode until the voltage

on the RCx terminal decays to the same level as voltage

applied to the PFD terminal. The time that the device oper-

ates in fast decay is approximated by:

After this Fast decay portion, the device switches to Slow

decay mode for the remainder of the fixed off-time period.