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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ST92195C датащи(PDF) 63 Page - STMicroelectronics |
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ST92195C датащи(HTML) 63 Page - STMicroelectronics |
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63 / 249 page  63/249 ST92195C/D - RESET AND CLOCK CONTROL UNIT (RCCU) 4.5 RESET CONTROL UNIT REGISTERS The RCCU consists of two registers. They are PCONF and SDRATH. Unless otherwise stated, unused register bits must be kept in their reset val- ue in order to avoid problems with the device be- haviour. PLL CONFIGURATION REGISTER (PCONF) R251 - Read/Write Register Page: 55 Reset value: 0000 0111 (07h) Bit 7= SRESEN. Software Reset Enable. 0: RCCU PLL and CSDU are turned off when a HALT instruction is performed. 1: RCCU will reset the microcontroller when a HALT instruction is performed. Bits 6:0= Reserved bits. Leave in their reset state. CLOCK SLOW DOWN UNIT RATIO REGISTER (SDRATH) R254 - Read/Write Register Page: 55 Reset value: 0010 0xxx (2xh) after software reset 0100 0xxx (4xh) after watchdog reset 0000 0000 (00h) after external reset Bit 7 = Reserved bit. Leave in its reset state. Bit 6 = WDGRES. Watchdog Reset. WDGRES is automatically set if the last reset was a watchdog Reset. This is a read only bit. Bit 5 = SFTRES. Software Reset. SFTRES is au- tomatically set if the last reset was a software Re- set. This is a read only bit. Bits 4:0 = Reserved bits. Please leave in their re- set state. 70 SRESEN 0 0 0 0 1 1 1 70 0 WDGRE S SFTRE S 00 x x x |
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