CS61581 datasheet(22/37 Pages) CIRRUS

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CS61581

DS211PP8

2.19

Control Register 3 (CR3): Address 0x14

QRSSPATH

When QRSSPATH = 0 the QRSS pattern will be output from the recovered data pins, RPOS,

RNEG (RDATA), and may be received at the transmitter inputs, TPOS, TNEG (TDATA). When

QRSSPATH = 1 the QRSS pattern will be output from the line transmitter and may be received

at the receiver.

E1_LH

E1 Long Haul

When E1_LH = 1 and SH/LH (CR2.0) = 0, the following functionality applies: Coder mode se-

lects HDB3 coding and decoding; when MATCHZ = 1, the output impedance of the transmitter

will be set to match impedances near 120

. ; the QRSS pattern is 215-1; the jitter attenuator is

adjusted for TBR12/13 compliance, with the knee in the frequency response at 1.25 Hz.

When E1_LH = 0 and SH/LH = 0, the following functionality applies: Coder mode selects B8ZS

coding and decoding; when MATCHZ = 1, the output impedance of the transmitter will be set to

match impedances near 100

. ; the QRSS pattern is 220-1; the jitter attenuator is adjusted for

AT&T 62411 compliance, with the knee in the frequency response at 4 Hz.

This bit is ignored if SH/LH = 1.

RST_QERR

Reset Data Pattern Error Count Register

Setting RST_QERR to “1” will clear the QRSS error count in the DPEC register.

This bit is automatically cleared and will read as “0.”

QDET

QRSS Detector Enable

When QDET = 1, the QRSS pattern detector is enabled. Errors detected and counted are stored

in the DPEC register (address 0x15).

INS_QERR

QRSS Error Insert

Setting INS_QERR to “1” and then “0” causes an error to be inserted in the output QRSS pat-

tern.

QSYNC/Test

QSYNC reads as “1” to indicate when the QRSS detector is synchronized to an input pattern.

QSYNC is only valid when QDET = 1 enabling the pattern detector.

When writing this register, this bit must be set to “0” for normal operation.

QGEN

QRSS Generator Enable

When QGEN = 1, the QRSS generator is enabled. The QRSS pattern is output at the

TTIP/TRING pins, or at the RPOS/RNEG (RDATA) pins, depending upon the state of the

QRSSPATH bit. Errors can be generated using the INS_QERR bit.

Test

Bit should be set to “0” for normal operation.

2.20

Data Pattern Error Count (DPEC): Address 0x15

DPEC[7:0]

Errors detected in the input QRSS pattern are counted and stored. This register saturates at

255 errors. The DPEC is cleared when the RST_QERR bit is written in the CR3 register.

7 (MSB)

0 (LSB)

QRSSPATH

E1_LH

RST_QERR

QDET

INS_QERR

QSYNC/Test

QGEN

Test

7 (MSB)

654321

0 (LSB)

DPEC.7

DPEC.6

DPEC.5

DPEC.4

DPEC.3

DPEC.2

DPEC.1

DPEC.0

CS61581

DS211F1

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