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CS42448 датащи(PDF) 47 Page - Cirrus Logic |
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CS42448 датащи(HTML) 47 Page - Cirrus Logic |
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47 / 70 page ![]() DS648PP2 47 6.5 INTERFACE FORMATS (ADDRESS 04H) 6.5.1 FREEZE CONTROLS (FREEZE) Default = 0 Function: This function will freeze the previous settings of, and allow modifications to be made to the channel mutes, the DAC and ADC Volume Control/Channel Invert registers without the changes taking effect until the FREEZE is disabled. To have multiple changes in these control port registers take effect si- multaneously, enable the FREEZE bit, make all register changes, then disable the FREEZE bit. 6.5.2 AUXILIARY DIGITAL INTERFACE FORMAT (AUX_DIF) Default = 0 0 - Left Justified 1 - I²S Function: This bit selects the digital interface format used for the AUX Serial Port. The required relationship be- tween the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options are detailed in Figures 21-22. 6.5.3 DAC DIGITAL INTERFACE FORMAT (DAC_DIF[2:0]) Default = 110 Function: These bits select the digital interface format used for the DAC Serial Port. The required relationship be- tween the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options are detailed in the section “CODEC Digital Interface Formats” on page 32. Refer to Table 9. “Serial Audio Interface Channel Allocations” on page 36. Ratio (xFs) MFreq2 MFreq1 MFreq0 Description SSM DSM QSM 00 0 1.0290 MHz to 12.8000 MHz 256 N/A N/A 00 1 1.5360 MHz to 19.2000 MHz 384 N/A N/A 01 0 2.0480 MHz to 25.6000 MHz 512 256 N/A 01 1 3.0720 MHz to 38.4000 MHz 768 384 N/A 1X X 4.0960 MHz to 51.2000 MHz 1024 512 256 Table 11. MCLK Frequency Settings for TDM & OLM Interface Formats 7 654 32 10 FREEZE AUX_DIF DAC_DIF2 DAC_DIF1 DAC_DIF0 ADC_DIF2 ADC_DIF1 ADC_DIF0 |
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