| поискавой системы для электроныых деталей |
|
CS42416 датащи(PDF) 22 Page - Cirrus Logic |
|
|
|||||||||||||||||||||||||||||
CS42416 датащи(HTML) 22 Page - Cirrus Logic |
|
22 / 67 page ![]() CS42416 22 3.5.4 One Line Mode(OLM) Configurations 3.5.4.1 OLM Config #1 One Line Mode Configuration #1 can support up to 6 channels of DAC data, and 6 channels of ADC data. This is the only configuration which will support up to 24-bit samples at a sampling frequency of 48 kHz on all channels for both the DAC and ADC. Register / Bit Settings Description Functional Mode Register (addr = 03h) Set DAC_FMx = ADC_FMx = 00,01,10 DAC_LRCK must equal ADC_LRCK; sample rate conversion not supported Set ADC_CLK_SEL = 0 Configure ADC_SDOUT to be clocked from the DAC_SP clocks. Interface Format Register (addr = 04h) Set DIFx bits to proper serial format Select the digital interface format when not in one line mode Set ADC_OLx bits = 00,01,10 Select ADC operating mode, see table below for valid combinations Set DAC_OLx bits = 00,01,10 Select DAC operating mode, see table below for valid combinations Misc. Control Register (addr = 05h) Set DAC_SP M/S = 1 Configure DAC Serial Port to master mode. Set ADC_SP M/S = 1 Configure ADC Serial Port to master mode. Set EXT ADC SCLK = 0 Identify external ADC clock source as ADC Serial Port. DAC Mode Not One Line Mode One Line Mode #1 One Line Mode #2 ADC Mode Not One Line Mode DAC_SCLK=64Fs DAC_LRCK=SSM/DSM/QSM DAC_SCLK=128Fs DAC_LRCK=SSM/DSM ADC_SCLK=64Fs ADC_LRCK=DAC_LRCK not valid One Line Mode #1 DAC_SCLK=128Fs DAC_LRCK=SSM/DSM ADC_SCLK=64Fs ADC_LRCK=DAC_LRCK DAC_SCLK=128Fs DAC_LRCK=SSM/DSM ADC_SCLK=64Fs ADC_LRCK=DAC_LRCK not valid One Line Mode #2 DAC_SCLK=256Fs DAC_LRCK=SSM ADC_SCLK=64Fs ADC_LRCK=DAC_LRCK not valid DAC_SCLK=256Fs DAC_LRCK=SSM ADC_SCLK=64Fs ADC_LRCK=DAC_LRCK SC LK _PO R T1 LRC K_PO R T1 SD IN_PO R T1 SC LK _PO R T2 LRC K_PO R T2 SD OUT1_PORT2 SD OUT2_PORT2 SD OUT3_PORT2 AD C_SC LK ADC _LR CK DAC_S CLK DAC_LR CK AD C_SD O UT DAC_SD IN1 DAC_SD IN2 DAC_SD IN3 RMCK AD CIN 1 AD CIN 2 MCLK SDO U T1 SDO U T2 LRC K SC LK 64Fs ADC Data 64Fs,128Fs, 256Fs DIG ITAL AU DIO PROC ESSOR CS5361 CS5361 MC LK Figure 13. OLM Configuration #1 CS42416 |
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |